qemu-armv7: Minimal changes to pass compiling qemu-v7 platform.

The ARM configuration files have been changed that we need more settings to run
Coreboot on qemu-v7.

Also fixed the incorrect Makefile settings that caused armv7 to try building
with armv8 cache.

BRANCH=none
BUG=none
TEST=make menuconfig # select qemu-armv7
     make # pass
     qemu... # successfully boots to ramstage.

Change-Id: I4040e86ad1ff6e8ebd07cfe387c3f5a0e8941800
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186080
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Hung-Te Lin <hungte@google.com>

src/cpu/armltd/Makefile.inc

@@ -1,2 +1,2 @@
 subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += cortex-a9
-subdirs-$(CONFIG_CPU_ARMLTD_CORTEX_A9) += armv8
+subdirs-$(CONFIG_CPU_ARMLTD_ARMV8) += armv8

src/mainboard/emulation/qemu-armv7/Kconfig

@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2013 Google Inc.
+## Copyright 2014 Google Inc.
 ##
 ## This software is licensed under the terms of the GNU General Public
 ## License version 2, as published by the Free Software Foundation, and
@@ -27,6 +27,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select CPU_ARMLTD_CORTEX_A9
 	select HAVE_UART_MEMORY_MAPPED
 	select HAVE_UART_SPECIAL
+	select BOOTBLOCK_CONSOLE
+	select EARLY_CONSOLE
+	select CONSOLE_SERIAL
+	select ARM_BOOTBLOCK_ARMV7
+	select ARM_ROMSTAGE_ARMV7
+	select ARM_RAMSTAGE_ARMV7
 	select BOARD_ROMSIZE_KB_4096
 
 config MAINBOARD_DIR
@@ -63,6 +69,14 @@ config DRAM_SIZE_MB
 # 0x0011_0000: CBFS data
 # 0x0100_0000: reserved for ramstage
 # 0x1000_0000: I/O map address
+#
+config STACK_TOP
+	hex
+	default 0x00100000
+
+config STACK_BOTTOM
+	hex
+	default 0x0007FF00
 
 config BOOTBLOCK_BASE
 	hex
@@ -76,6 +90,10 @@ config RAMSTAGE_BASE
 	hex
 	default SYS_SDRAM_BASE
 
+config BOOTBLOCK_ROM_OFFSET
+	hex
+	default 0x0
+
 config CBFS_HEADER_ROM_OFFSET
 	hex
 	default 0x0100000