From f2b7c5bead1ac43cb2cd617fd8a6e71ba3a7fe63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 22 Jul 2016 00:01:33 +0300 Subject: [PATCH] UPSTREAM: intel/haswell: Remove useless MTRR clear At this state, variable MTRRs are disabled. We overwrite this MTRR entry before they are re-enabled. Change-Id: Ieedf90f65514d848905626e75be496e08f710d91 Original-Signed-off-by: Kysti Mlkki Original-Reviewed-on: https://review.coreboot.org/15794 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/362767 Reviewed-by: Furquan Shaikh --- src/cpu/intel/haswell/cache_as_ram.inc | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index fe595fbd22..9cdb176ea4 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -209,14 +209,6 @@ before_romstage: andl $~1, %eax wrmsr - /* Clear MTRR that was used to cache MRC */ - xorl %eax, %eax - xorl %edx, %edx - movl $MTRR_PHYS_BASE(2), %ecx - wrmsr - movl $MTRR_PHYS_MASK(2), %ecx - wrmsr - post_code(0x33) /* Enable cache. */