diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb
index 9de1b75f50..8df5c9843b 100644
--- a/src/mainboard/emulation/qemu-riscv/devicetree.cb
+++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb
@@ -2,4 +2,9 @@
 
 chip mainboard/emulation/qemu-riscv
 	device cpu_cluster 0 on end
+
+	device domain 0 on
+		ops qemu_riscv_pci_domain_ops
+		device pci 00.0 on end
+	end
 end
diff --git a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
index eb0e9f3440..f36491c50c 100644
--- a/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h
@@ -1,9 +1,16 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #define QEMU_VIRT_CLINT		0x02000000
+#define QEMU_VIRT_PCIE_PIO	0x03000000
 #define QEMU_VIRT_PLIC		0x0c000000
 #define QEMU_VIRT_UART0		0x10000000
 #define QEMU_VIRT_VIRTIO	0x10001000
 #define QEMU_VIRT_FW_CFG	0x10100000
 #define QEMU_VIRT_FLASH		0x20000000
+#define QEMU_VIRT_PCIE_ECAM	0x30000000
+#define QEMU_VIRT_PCIE_ECAM_SIZE 0x10000000
+#define QEMU_VIRT_PCIE_MMIO_BASE  0x40000000
+#define QEMU_VIRT_PCIE_MMIO_LIMIT 0x7fffffff
 #define QEMU_VIRT_DRAM		0x80000000
+#define QEMU_VIRT_PCIE_MMIO_HIGH_BASE  0x300000000ULL
+#define QEMU_VIRT_PCIE_MMIO_HIGH_LIMIT 0x3ffffffffULL
diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c
index 61e8f98925..e801d14ba7 100644
--- a/src/mainboard/emulation/qemu-riscv/mainboard.c
+++ b/src/mainboard/emulation/qemu-riscv/mainboard.c
@@ -2,16 +2,52 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci.h>
 #include <symbols.h>
 #include <cbmem.h>
+#include <mainboard/addressmap.h>
+
+static void qemu_riscv_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+	int index = 0;
+
+	/* PCI I/O port window */
+	res = new_resource(dev, index++);
+	res->limit = 0xffff;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
+
+	/* 32-bit PCI MMIO window */
+	res = new_resource(dev, index++);
+	res->base = QEMU_VIRT_PCIE_MMIO_BASE;
+	res->limit = QEMU_VIRT_PCIE_MMIO_LIMIT;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
+
+	/*
+	 * NOTE: 64-bit MMIO window (0x300000000-0x3ffffffff) is omitted
+	 * because OpenSBI 1.1 (bundled with coreboot) does not add PMP
+	 * entries for it, causing S-mode load access faults.  All BARs
+	 * will be assigned in the 32-bit window which is plenty for the
+	 * QEMU virt machine's typical device set.
+	 */
+
+	/* ECAM config space (fixed MMIO) */
+	mmio_range(dev, index++, QEMU_VIRT_PCIE_ECAM, QEMU_VIRT_PCIE_ECAM_SIZE);
+
+	/* DRAM */
+	ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top());
+}
+
+struct device_operations qemu_riscv_pci_domain_ops = {
+	.read_resources    = qemu_riscv_domain_read_resources,
+	.set_resources     = pci_domain_set_resources,
+	.scan_bus          = pci_host_bridge_scan_bus,
+};
 
 static void mainboard_enable(struct device *dev)
 {
-	if (!dev) {
+	if (!dev)
 		die("No dev0; die\n");
-	}
-
-	ram_from_to(dev, 0, (uintptr_t)_dram, cbmem_top());
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/emulation/qemu-riscv/mmio.c b/src/mainboard/emulation/qemu-riscv/mmio.c
index 86fc626d14..9c38a74741 100644
--- a/src/mainboard/emulation/qemu-riscv/mmio.c
+++ b/src/mainboard/emulation/qemu-riscv/mmio.c
@@ -3,4 +3,4 @@
 #include <types.h>
 #include <mainboard/addressmap.h>
 
-uintptr_t io_port_mmio_base = QEMU_VIRT_FW_CFG;
+uintptr_t io_port_mmio_base = QEMU_VIRT_PCIE_PIO;