New mechanism to define SRAM/memory map with automatic bounds checking

This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213370

src/lib/Makefile.inc

@@ -117,6 +117,14 @@ ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
 romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c
 
+ifneq ($(CONFIG_ARCH_X86),y)
+# X86 bootblock and romstage use custom ldscripts that are all glued together,
+# so we need to exclude it here or it would pick these up as well
+bootblock-y += bootblock.ld
+romstage-y += romstage.ld
+endif
+ramstage-y += ramstage.ld
+
 smm-y += cbfs.c memcmp.c
 smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c

src/lib/bootblock.ld

@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file is included inside a SECTIONS block */
+
+.bootblock . : {
+	_program = .;
+	_bootblock = .;
+	*(.text._start);
+	*(.text.stage_entry);
+	KEEP(*(.id));
+	*(.text);
+	*(.text.*);
+	*(.rodata);
+	*(.rodata.*);
+	*(.data);
+	*(.data.*);
+	*(.bss);
+	*(.bss.*);
+	*(.sbss);
+	*(.sbss.*);
+	_ebootblock = .;
+	_eprogram = .;
+} : to_load = 0xff
+
+/DISCARD/ : {
+	*(.comment)
+	*(.note)
+	*(.comment.*)
+	*(.note.*)
+	*(.ARM.*)
+}

src/lib/cbfs_spi.c

@@ -25,6 +25,7 @@
 
 #include <cbfs.h>
 #include <spi_flash.h>
+#include <symbols.h>
 
 /* SPI flash as CBFS media. */
 struct cbfs_spi_context {
@@ -80,8 +81,8 @@ static int init_cbfs_media_context(void)
 		if (!spi_context.spi_flash_info)
 			return -1;
 
-		spi_context.buffer.buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
-		spi_context.buffer.size = CONFIG_CBFS_CACHE_SIZE;
+		spi_context.buffer.buffer = (void *)_cbfs_cache;
+		spi_context.buffer.size = _cbfs_cache_size;
 	}
 	return 0;
 

src/lib/cbmem_console.c

@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <arch/early_variables.h>
+#include <symbols.h>
 #include <string.h>
 
 /*
@@ -40,11 +41,9 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL;
 /*
  * While running from ROM, before DRAM is initialized, some area in cache as
  * ram space is used for the console buffer storage. The size and location of
- * the area are defined in the config.
+ * the area are defined by the linker script with _(e)preram_cbmem_console.
  */
 
-extern struct cbmem_console preram_cbmem_console;
-
 /*
  * Once DRAM is initialized and the cache as ram mode is disabled, while still
  * running from ROM, the console buffer in the cache as RAM area becomes
@@ -121,8 +120,7 @@ static inline void init_console_ptr(void *storage, u32 total_space)
 void cbmemc_init(void)
 {
 #ifdef __PRE_RAM__
-	init_console_ptr(&preram_cbmem_console,
-			 CONFIG_CONSOLE_PRERAM_BUFFER_SIZE);
+	init_console_ptr(_preram_cbmem_console, _preram_cbmem_console_size);
 #else
 	/*
 	 * Initializing before CBMEM is available, use static buffer to store

src/lib/ramstage.ld

@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file is included inside a SECTIONS block */
+
+/* First we place the code and read only data (typically const declared).
+ * This could theoretically be placed in rom.
+ */
+.text : {
+	_program = .;
+	_ramstage = .;
+	_text = .;
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+	. = ALIGN(16);
+	_etext = .;
+} : to_load
+
+#ifdef CONFIG_COVERAGE
+.ctors : {
+	. = ALIGN(0x100);
+	__CTOR_LIST__ = .;
+	KEEP(*(.ctors));
+	LONG(0);
+	LONG(0);
+	__CTOR_END__ = .;
+}
+#endif
+
+/* TODO: align data sections to cache lines? (is that really useful?) */
+.rodata : {
+	_rodata = .;
+	. = ALIGN(8);
+
+	/* If any changes are made to the driver start/symbols or the
+	 * section names the equivalent changes need to made to
+	 * rmodule.ld. */
+	console_drivers = .;
+	KEEP(*(.rodata.console_drivers));
+	econsole_drivers = . ;
+	. = ALIGN(8);
+	pci_drivers = . ;
+	KEEP(*(.rodata.pci_driver));
+	epci_drivers = . ;
+	cpu_drivers = . ;
+	KEEP(*(.rodata.cpu_driver));
+	ecpu_drivers = . ;
+	_bs_init_begin = .;
+	KEEP(*(.bs_init));
+	_bs_init_end = .;
+
+	*(.rodata)
+	*(.rodata.*)
+	/* kevinh/Ispiri - Added an align, because the objcopy tool
+	 * incorrectly converts sections that are not long word aligned.
+	 */
+	 . = ALIGN(8);
+
+	_erodata = .;
+}
+
+.data : {
+	/* Move to different cache line to avoid false sharing with .rodata. */
+	. = ALIGN(64);	/* May not be actual line size, not that important. */
+	_data = .;
+	*(.data)
+	*(.data.*)
+	_edata = .;
+}
+
+.bss . : {
+	_bss = .;
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	_ebss = .;
+}
+
+.heap . : {
+	_heap = .;
+	/* Reserve CONFIG_HEAP_SIZE bytes for the heap */
+	. += CONFIG_HEAP_SIZE ;
+	. = ALIGN(4);
+	_eheap = .;
+	_eramstage = .;
+	_eprogram = .;
+}
+
+/* Discard the sections we don't need/want */
+
+/DISCARD/ : {
+	*(.comment)
+	*(.note)
+	*(.note.*)
+}

src/lib/rmodule.ld

@@ -20,18 +20,21 @@ SECTIONS
 
 	.payload :  {
 		/* C code of the module. */
-		_ram_seg = .;
-		*(.textfirst);
+		_program = .;
+		*(.text._start);
+		*(.text.stage_entry);
 		*(.text);
 		*(.text.*);
 		/* C read-only data. */
 		. = ALIGN(16);
 
+#ifdef CONFIG_COVERAGE
 		__CTOR_LIST__ = .;
 		*(.ctors);
 		LONG(0);
 		LONG(0);
 		__CTOR_END__ = .;
+#endif
 
 		/* The driver sections are to allow linking coreboot's
 		 * ramstage with the rmodule linker. Any changes made in
@@ -68,6 +71,7 @@ SECTIONS
 		. = ALIGN(8);
 
 		/* Data section. */
+		. = ALIGN(64);	/* Mirror cache line alignment from ramstage. */
 		_sdata = .;
 		*(.data);
 		*(.data.*);
@@ -95,7 +99,7 @@ SECTIONS
 		_heap = .;
 		. = . + __heap_size;
 		_eheap = .;
-		_eram_seg = .;
+		_eprogram = .;
 	}
 
 	/DISCARD/ : {

src/lib/romstage.ld

@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file is included inside a SECTIONS block */
+
+.text . : {
+	_program = .;
+	_romstage = .;
+	*(.text._start);
+	*(.text.stage_entry);
+	*(.text);
+	*(.text.*);
+} : to_load
+
+.data . : {
+	*(.rodata);
+	*(.rodata.*);
+	*(.data);
+	*(.data.*);
+	. = ALIGN(8);
+}
+
+.bss . : {
+	. = ALIGN(8);
+	_bss = .;
+	*(.bss)
+	*(.bss.*)
+	*(.sbss)
+	*(.sbss.*)
+	_ebss = .;
+	_eromstage = .;
+	_eprogram = .;
+}
+
+/* Discard the sections we don't need/want */
+/DISCARD/ : {
+	*(.comment)
+	*(.note)
+	*(.comment.*)
+	*(.note.*)
+	*(.eh_frame);
+}

src/lib/selfboot.c

@@ -27,6 +27,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+#include <symbols.h>
 #include <cbfs.h>
 #include <lib.h>
 #if CONFIG_COLLECT_TIMESTAMPS
@@ -38,12 +39,8 @@
 #define MAX_ADDR -1UL
 #endif
 
-/* from ramstage.ld: */
-extern unsigned char _ram_seg;
-extern unsigned char _eram_seg;
-
-static const unsigned long lb_start = (unsigned long)&_ram_seg;
-static const unsigned long lb_end = (unsigned long)&_eram_seg;
+static const unsigned long lb_start = (unsigned long)&_program;
+static const unsigned long lb_end = (unsigned long)&_eprogram;
 
 struct segment {
 	struct segment *next;