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soc/intel/xeon_sp/skx: Enable x86_64

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On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of
the address space. Most of the PCI BARs reside in high MMIO, not
reachable by x86_32 coreboot.

Add support for x86_64 coreboot and confirm that all supported boards
are booting without errors. This is done by:

- converting all occurrences of VOID * to UINT32 to make sure that
  FSP UPDs do not change when pointers are 8byte wide.
- Drop SetupStructPtr as it's unused within FSP and coreboot

TEST: Booted on ocp/tiogapass to Linux. No errors were observed.

Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Patrick Rudolph 2024-12-30 11:27:44 +01:00 • committed by Matt DeVillier
commit f13b4ca285
3 changed files with 36 additions and 33 deletions
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47
src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
View file

@ -37,6 +37,9 @@ are permitted provided that the following conditions are met:
#pragma pack(1)
/* Must not use VOID * since that would break x86_64 coreboot support! */
#define PTR_32B(type) UINT32
/**
FSP Header Version Number
**/
@ -261,7 +264,7 @@ typedef struct {
/**
GPIOTABLE_CONFIG:
GpioTable - Base Address of the Gpio Table declared by the
bootloader.
bootloader. Pointer to UPD_GPIO_INIT_CONFIG.
Default: NULL
NumberofEntries - Number of Entries in the GPIO Table provided
Default: 0
@ -269,8 +272,8 @@ typedef struct {
configuration using default GPIO_INIT_CONFIG tables
**/
typedef struct {
UPD_GPIO_INIT_CONFIG *GpioTable;
UINT32 NumberOfEntries;
PTR_32B(UPD_GPIO_INIT_CONFIG) GpioTablePtr;
UINT32 NumberOfEntries;
} GPIOTABLE_CONFIG;
/**
@ -293,7 +296,7 @@ typedef struct {
/**
IIOBIFURCATION_CONFIG:
IIoBifurcationTable - Base Address of the IIO Bifurcation table
declared by the bootloader
declared by the bootloader. Pointer to UPD_IIO_BIFURCATION_DATA_ENTRY.
Default: NULL
NumberofEntries - Number of Entries in the IIO Bifurcation Table
Default: 0
@ -301,8 +304,8 @@ typedef struct {
bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables
**/
typedef struct {
UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable;
UINT32 NumberOfEntries;
PTR_32B(UPD_IIO_BIFURCATION_DATA_ENTRY) IIoBifurcationTablePtr;
UINT32 NumberOfEntries;
} IIOBIFURCATION_CONFIG;
/**
@ -381,13 +384,12 @@ typedef struct {
/**
PCIEPORT_CONFIG:
PciePortConfiguration - Pointer to an array of PCIe port configuration structures
as declared above
as declared above. Pointer to UPD_PCI_PORT_CONFIG.
NumberOfEntries - Number of elements in the PciePortConfiguration Array
**/
typedef struct {
UPD_PCI_PORT_CONFIG *ConfigurationTable;
UINT16 NumberOfEntries;
PTR_32B(UPD_PCI_PORT_CONFIG) ConfigurationTablePtr;
UINT16 NumberOfEntries;
} IIOPCIPORT_CONFIG;
/**
@ -412,12 +414,13 @@ typedef struct {
/**
IIORESOURCE_CONFIG:
ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array
ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array.
Pointer to UPD_IIO_STACK_RESOURCE_CONFIG.
NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array
**/
typedef struct {
UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable;
UINT16 NumberOfEntries;
PTR_32B(UPD_IIO_STACK_RESOURCE_CONFIG) ResourceTablePtr;
UINT16 NumberOfEntries;
} IIORESOURCE_CONFIG;
/**
@ -436,6 +439,7 @@ typedef struct {
/**
PCHPCIPORT_CONFIG:
PciPortConfig - Pointer to an array of PCH PCI Ports to be configured
Pointer to UPD_PCH_PCIE_PORT.
RootPortFunctionSwapping - Disable root port swapping based on device
connection status
PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage
@ -446,10 +450,10 @@ typedef struct {
NumberOfEntries - Number of entries in the PCH PCI Port configuration
**/
typedef struct {
UPD_PCH_PCIE_PORT *PciPortConfig;
UINT8 RootPortFunctionSwapping;
UINT8 PciePllSsc;
UINT16 NumberOfEntries;
PTR_32B(UPD_PCH_PCIE_PORT) PciPortConfigPtr;
UINT8 RootPortFunctionSwapping;
UINT8 PciePllSsc;
UINT16 NumberOfEntries;
} PCHPCIPORT_CONFIG;
/** FSP-M Configuration
@ -507,12 +511,7 @@ typedef struct {
**/
UINT8 BoardId;
UINT8 reserved2[24];
/** Offset 0x00C2 **/
VOID *SetupStructPtr;
UINT8 reserved3[20];
UINT8 reserved2[48];
/** Offset 0x00DA - IioPciConfig
IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero.
@ -529,7 +528,7 @@ typedef struct {
**/
IIORESOURCE_CONFIG IioResourceConfig;
UINT8 reserved4[3];
UINT8 reserved3[3];
/** Offset 0x00F1 - DCI Enable
Enable / Disable DCI