From f0f66be2c345b4f92f7eb4d0a4852e3702b81397 Mon Sep 17 00:00:00 2001 From: Pranava Y N Date: Fri, 28 Feb 2025 16:11:46 +0530 Subject: [PATCH] mb/google/brya/bujia: Enable RTD3 for SSD Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. BUG=b:391612392 TEST=Run suspend_stress_test on Bujia and verify that the device suspends to S0ix. Change-Id: Idee14e7d4df0a9cf8b06b33a52016c1b9228e459 Signed-off-by: Pranava Y N Reviewed-on: https://review.coreboot.org/c/coreboot/+/86644 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/bujia/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 6db60acb67..370c0520c6 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -119,6 +119,13 @@ chip soc/intel/alderlake .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "srcclk_pin" = "0" + device generic 0 on end + end end #NVME device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end