From f0a1366d328f84e720fe7768cecfe57b3e7dca79 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Thu, 3 Oct 2013 12:07:59 +0800 Subject: [PATCH] beltino: get ChromeOS up and running BRANCH=none BUG=none TEST=boot ChromeOS on Beltino Signed-off-by: Stefan Reinauer Change-Id: I6db35b0675f8c1c3d81d34c3b28adf8519de224f Reviewed-on: https://chromium-review.googlesource.com/171554 Reviewed-by: Duncan Laurie Reviewed-by: Aaron Durbin Tested-by: Stefan Reinauer Commit-Queue: Stefan Reinauer --- src/mainboard/google/beltino/chromeos.c | 28 +--------------------- src/mainboard/google/beltino/devicetree.cb | 2 +- src/mainboard/google/beltino/romstage.c | 13 ++++++++-- 3 files changed, 13 insertions(+), 30 deletions(-) diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 51d625b82c..021ee38662 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -24,11 +24,6 @@ #include #include -#if CONFIG_EC_GOOGLE_CHROMEEC -#include "ec.h" -#include -#endif - #ifndef __PRE_RAM__ #include @@ -38,13 +33,7 @@ static int get_lid_switch(void) { -#if CONFIG_EC_GOOGLE_CHROMEEC - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - - return !!(ec_switches & EC_SWITCH_LID_OPEN); -#else - return 0; -#endif + return 1; } static void fill_lb_gpio(struct lb_gpio *gpio, int num, @@ -90,22 +79,7 @@ int get_developer_mode_switch(void) * the other is driven by Servo. */ int get_recovery_mode_switch(void) { -#if CONFIG_EC_GOOGLE_CHROMEEC - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - u32 ec_events; - - /* If a switch is set, we don't need to look at events. */ - if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) - return 1; - - /* Else check if the EC has posted the keyboard recovery event. */ - ec_events = google_chromeec_get_events_b(); - - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -#else return 0; -#endif } int get_write_protect_state(void) diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 4a2bca4476..0f8549bb5f 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -127,7 +127,7 @@ chip northbridge/intel/haswell device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x2f8 + io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.4 on # Environment Controller diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 7d2ee23ba4..eeb756348a 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -29,6 +29,8 @@ #include #include #include "gpio.h" +#include "superio/ite/it8772f/it8772f.h" +#include "superio/ite/it8772f/early_serial.c" const struct rcba_config_instruction rcba_config[] = { @@ -88,8 +90,8 @@ void mainboard_romstage_entry(unsigned long bist) temp_mmio_base: 0xfed08000, system_type: 5, /* ULT */ tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xa0, 0x00, 0xa2, 0x00 }, - ec_present: 1, + spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, + ec_present: 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel @@ -136,6 +138,13 @@ void mainboard_romstage_entry(unsigned long bist) .bist = bist, }; + /* Early SuperIO setup */ + it8772f_kill_watchdog(); + it8772f_ac_resume_southbridge(); + pch_enable_lpc(); + it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1), + CONFIG_TTYS0_BASE); + /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); }