diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
index 40635bde30..ec5d3c03e9 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb
@@ -155,7 +155,8 @@ chip soc/intel/alderlake
 
 			}"
 			chip drivers/pcie/generic
-				register "wake_gpe" = "GPE0_PME_B0"
+				register "wake_gpe" = "GPE0_LAN_WAK"
+				register "wake_deepest" = "ACPI_S3"
 				device generic 0 on end
 			end
 			smbios_slot_desc				"SlotTypePciExpressGen4x1"
@@ -172,7 +173,8 @@ chip soc/intel/alderlake
 				.PcieRpL1Substates			= L1_SS_L1_2,
 			}"
 			chip drivers/pcie/generic
-				register "wake_gpe" = "GPE0_PME_B0"
+				register "wake_gpe" = "GPE0_LAN_WAK"
+				register "wake_deepest" = "ACPI_S3"
 				device generic 0 on end
 			end
 			smbios_slot_desc				"SlotTypePciExpressGen3X4"
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
index bddabb14db..0c0173cb40 100644
--- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
+++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c
@@ -20,6 +20,7 @@ const struct pad_config gpio_table[] = {
 	/* General Purpose I/O Deep */
 	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),				/* Battery Low */
 	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),				/* Charger Connected */
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),				/* LAN Wake */
 	PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),				/* Power Button */
 	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),				/* Sleep S3 */
 	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),				/* Sleep S4 */
@@ -99,7 +100,6 @@ const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPP_F7, 0, PLTRST),					/* MCRO LDO		[ Disabled / Bypass   ] */
 	PAD_CFG_GPO(GPD7, 0, PLTRST),					/* RTC Clock Delay	[ Disabled / 95ms     ] */
 
-	PAD_NC(GPD2, NONE),
 	PAD_NC(GPD6, NONE),
 	PAD_NC(GPD9, NONE),
 	PAD_NC(GPD11, NONE),