From f020befeb4f50dd8139875a7730dddff264c92bc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Mon, 22 Aug 2016 19:37:15 +0200
Subject: [PATCH] UPSTREAM: arch/riscv: Delegate exceptions to supervisor mode
 if appropriate

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16160
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd
Reviewed-on: https://chromium-review.googlesource.com/374132
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/arch/riscv/virtual_memory.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index bea552de86..98b7edca4e 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -208,4 +208,14 @@ void mstatus_init(void)
 
 	clear_csr(mip, MIP_MSIP);
 	set_csr(mie, MIP_MSIP);
+
+	/* Configure which exception causes are delegated to supervisor mode */
+	set_csr(medeleg,  (1 << CAUSE_MISALIGNED_FETCH)
+			| (1 << CAUSE_FAULT_FETCH)
+			| (1 << CAUSE_ILLEGAL_INSTRUCTION)
+			| (1 << CAUSE_BREAKPOINT)
+			| (1 << CAUSE_FAULT_LOAD)
+			| (1 << CAUSE_FAULT_STORE)
+			| (1 << CAUSE_USER_ECALL)
+	);
 }