vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to version WCL.3515.03
Update Wildcatlake FSP headers to align with the FSP version WCL.3515.03. BUG=b:475358197 TEST=Build the ocelot CB with the latest header changes. Change-Id: I1232523e662d91cf43e7ed6bcc4fbefeaf8447e9 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90753 Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Avi Uday <aviuday@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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4 changed files with 3435 additions and 446 deletions
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@ -1,6 +1,6 @@
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/** @file
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Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2026, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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@ -312,7 +312,8 @@ typedef struct _PPR_RESULT_COLUMNS_HOB {
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- DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth
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- DIMM_INFO: Removed SpdModuleMemoryBusWidth
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- MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing
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<b>Revision 4:</b>
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- Added FailingChannelMask
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**/
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typedef struct {
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UINT8 Revision;
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@ -363,6 +364,7 @@ typedef struct {
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UINT8 MaxRankCapacity; ///< Maximum possible rank capacity in [GB]
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UINT16 PprFailingChannelBitMask; ///< PPR failing channel mask
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BOOLEAN PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
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UINT8 FailingChannelMask; ///< Limp Home mode failing channel bitmask
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} MEMORY_INFO_DATA_HOB;
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/**
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@ -387,6 +389,9 @@ typedef struct {
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PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
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PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
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BOOLEAN MrcBasicMemoryTestPass;
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UINT8 Reserved1[3]; // Reserved for alignment
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UINT64 BiosPeiMemoryBaseAddress;
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UINT64 BiosPeiMemoryLength;
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} MEMORY_PLATFORM_DATA;
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typedef struct {
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