vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to version WCL.3515.03

Update Wildcatlake FSP headers to align with the FSP version WCL.3515.03.

BUG=b:475358197
TEST=Build the ocelot CB with the latest header changes.

Change-Id: I1232523e662d91cf43e7ed6bcc4fbefeaf8447e9
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90753
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sowmya V 2026-01-14 11:54:47 +05:30 committed by Matt DeVillier
commit f01e11ac5c
4 changed files with 3435 additions and 446 deletions

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@ -1,6 +1,6 @@
/** @file
Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2026, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

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@ -312,7 +312,8 @@ typedef struct _PPR_RESULT_COLUMNS_HOB {
- DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth
- DIMM_INFO: Removed SpdModuleMemoryBusWidth
- MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing
<b>Revision 4:</b>
- Added FailingChannelMask
**/
typedef struct {
UINT8 Revision;
@ -363,6 +364,7 @@ typedef struct {
UINT8 MaxRankCapacity; ///< Maximum possible rank capacity in [GB]
UINT16 PprFailingChannelBitMask; ///< PPR failing channel mask
BOOLEAN PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
UINT8 FailingChannelMask; ///< Limp Home mode failing channel bitmask
} MEMORY_INFO_DATA_HOB;
/**
@ -387,6 +389,9 @@ typedef struct {
PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
BOOLEAN MrcBasicMemoryTestPass;
UINT8 Reserved1[3]; // Reserved for alignment
UINT64 BiosPeiMemoryBaseAddress;
UINT64 BiosPeiMemoryLength;
} MEMORY_PLATFORM_DATA;
typedef struct {