diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 1568e5b595..a925cf09a0 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -88,6 +88,7 @@ config SOC_INTEL_ALDERLAKE
 	select SOC_INTEL_COMMON_FEATURE_ESPI
 	select SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_PMUTIL
+	select SOC_INTEL_COMMON_FEATURE_SMIHANDLER
 	select SOC_INTEL_COMMON_FEATURE_SOUNDWIRE
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN
 	select SOC_INTEL_COMMON_FEATURE_SPI_DEVFN_PSF
diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk
index 210d84592d..45c374849d 100644
--- a/src/soc/intel/alderlake/Makefile.mk
+++ b/src/soc/intel/alderlake/Makefile.mk
@@ -39,7 +39,6 @@ ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c
 
 smm-y += elog.c
 smm-y += p2sb.c
-smm-y += smihandler.c
 smm-y += xhci.c
 
 ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h
index 15ec661870..27134c74a5 100644
--- a/src/soc/intel/alderlake/include/soc/pci_devs.h
+++ b/src/soc/intel/alderlake/include/soc/pci_devs.h
@@ -283,6 +283,7 @@
 #define PCI_DEVFN_UART1		PCH_DEVFN_UART1
 #define PCI_DEVFN_UART2		PCH_DEVFN_UART2
 #define SOC_GSPI_DEVFN(n)	PCH_DEVFN_GSPI##n
+#define SOC_PMC_DEV		PCH_DEV_PMC
 
 #endif
 
diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c
deleted file mode 100644
index e1fc5a03ad..0000000000
--- a/src/soc/intel/alderlake/smihandler.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <device/pci_def.h>
-#include <intelblocks/smihandler.h>
-#include <soc/soc_chip.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-
-int smihandler_soc_disable_busmaster(pci_devfn_t dev)
-{
-	/* Skip disabling PMC bus master to keep IO decode enabled */
-	if (dev == PCH_DEV_PMC)
-		return 0;
-	return 1;
-}
-
-const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
-	[SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep,
-	[APM_STS_BIT] = smihandler_southbridge_apmc,
-	[PM1_STS_BIT] = smihandler_southbridge_pm1,
-	[GPE0_STS_BIT] = smihandler_southbridge_gpe0,
-	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
-	[ESPI_SMI_STS_BIT] = smihandler_southbridge_espi,
-	[MCSMI_STS_BIT] = smihandler_southbridge_mc,
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
-	[TCO_STS_BIT] = smihandler_southbridge_tco,
-#endif
-	[PERIODIC_STS_BIT] = smihandler_southbridge_periodic,
-	[MONITOR_STS_BIT] = smihandler_southbridge_monitor,
-};