erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

nb/intel/x4x: Implement resume from S3 suspend

Browse source 
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.

Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).

Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Arthur Heymans 2016-12-30 21:07:18 +01:00 • committed by Nico Huber
commit ef7e98a2ac
7 changed files with 201 additions and 198 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
View file

@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS
select REALTEK_8168_RESET
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
config MMCONF_BASE_ADDRESS
hex

7
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
View file

@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist)
// ch0 ch1
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
u8 boot_path = 0;
u8 s3_resume;
/* Disable watchdog timer */
RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
@ -151,16 +152,18 @@ void mainboard_romstage_entry(unsigned long bist)
x4x_early_init();
s3_resume = southbridge_detect_s3_resume();
if (s3_resume)
boot_path = BOOT_PATH_RESUME;
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
sdram_initialize(boot_path, spd_addrmap);
quick_ram_check();
cbmem_initialize_empty();
printk(BIOS_DEBUG, "Memory initialized\n");
x4x_late_init();
x4x_late_init(s3_resume);
printk(BIOS_DEBUG, "x4x late init complete\n");