From ef61d4d9254e9b9733933a124012e853cc56864d Mon Sep 17 00:00:00 2001 From: Kun Liu Date: Tue, 8 Apr 2025 20:58:51 +0800 Subject: [PATCH] mb/google/nissa/var/telith: Support x32 memory configuration Use GPP_E19 level to determine whether x32 memory configuration is supported. BUG=b:405303038 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I969fea2aba858f76870c1a31ad4bd884ec9b6ff3 Signed-off-by: Kun Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/87212 Reviewed-by: Jayvik Desai Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Qinghong Zeng Reviewed-by: Dinesh Gehlot --- src/mainboard/google/brya/Kconfig | 1 + .../google/brya/variants/telith/Makefile.mk | 1 + .../google/brya/variants/telith/gpio.c | 5 +++++ .../google/brya/variants/telith/memory.c | 20 +++++++++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 src/mainboard/google/brya/variants/telith/memory.c diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 5331f0e42f..50a2959022 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -631,6 +631,7 @@ config BOARD_GOOGLE_TELITH select DRIVERS_INTEL_MIPI_CAMERA select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select SOC_INTEL_TWINLAKE + select ENFORCE_MEM_CHANNEL_DISABLE config BOARD_GOOGLE_TEREID select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/telith/Makefile.mk b/src/mainboard/google/brya/variants/telith/Makefile.mk index e7ef021a8d..b67f3087de 100644 --- a/src/mainboard/google/brya/variants/telith/Makefile.mk +++ b/src/mainboard/google/brya/variants/telith/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c index 0043111d74..75f7617655 100644 --- a/src/mainboard/google/brya/variants/telith/gpio.c +++ b/src/mainboard/google/brya/variants/telith/gpio.c @@ -69,6 +69,9 @@ static const struct pad_config override_gpio_table[] = { /* R7 : DMIC_DATA_1A ==> NC */ PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ /* BT_I2S_BCLK */ PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), @@ -112,6 +115,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E19, DN_20K, LOCK_CONFIG), }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/telith/memory.c b/src/mainboard/google/brya/variants/telith/memory.c new file mode 100644 index 0000000000..51a7ff504c --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/memory.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E19 High -> One RAM Chip + * GPP_E19 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E19)) { + /* Disable all other channels except first two on each controller */ + return (BIT(2) | BIT(3)); + } + + return 0; +}