From ef2a7121067f1aec0390ea7a571e28e32a8f9a1e Mon Sep 17 00:00:00 2001
From: "Ronald G. Minnich" <rminnich@gmail.com>
Date: Fri, 19 Jan 2001 17:02:36 +0000
Subject: [PATCH] added files for 440bx

---
 src/mainboard/gigabit/ga-6bxc/Config     |  15 +++
 src/northbridge/intel/440bx/Config       |   3 +
 src/southbridge/intel/piix4e/Config      |   1 +
 src/superio/ITE/it8671f/setup_serial.inc | 154 +++++++++++++++++++++++
 4 files changed, 173 insertions(+)
 create mode 100644 src/mainboard/gigabit/ga-6bxc/Config
 create mode 100644 src/northbridge/intel/440bx/Config
 create mode 100644 src/southbridge/intel/piix4e/Config
 create mode 100644 src/superio/ITE/it8671f/setup_serial.inc

diff --git a/src/mainboard/gigabit/ga-6bxc/Config b/src/mainboard/gigabit/ga-6bxc/Config
new file mode 100644
index 0000000000..66acee8246
--- /dev/null
+++ b/src/mainboard/gigabit/ga-6bxc/Config
@@ -0,0 +1,15 @@
+northbridge intel/440bx
+southbridge intel/piix4e
+
+superio ITE/it8671f
+
+option ENABLE_FIXED_AND_VARIABLE_MTRRS
+option FINAL_MAINBOARD_FIXUP
+option HAVE_PIRQ_TABLE
+option PIIX4_DEVFN=0x38
+
+object mainboard.o
+object irq_tables.o
+
+cpu p5
+cpu p6
diff --git a/src/northbridge/intel/440bx/Config b/src/northbridge/intel/440bx/Config
new file mode 100644
index 0000000000..d1761d6401
--- /dev/null
+++ b/src/northbridge/intel/440bx/Config
@@ -0,0 +1,3 @@
+raminit northbridge/intel/440bx/raminit.inc
+
+object northbridge.o
diff --git a/src/southbridge/intel/piix4e/Config b/src/southbridge/intel/piix4e/Config
new file mode 100644
index 0000000000..094297c0ab
--- /dev/null
+++ b/src/southbridge/intel/piix4e/Config
@@ -0,0 +1 @@
+object southbridge.o
diff --git a/src/superio/ITE/it8671f/setup_serial.inc b/src/superio/ITE/it8671f/setup_serial.inc
new file mode 100644
index 0000000000..e4a916895f
--- /dev/null
+++ b/src/superio/ITE/it8671f/setup_serial.inc
@@ -0,0 +1,154 @@
+/*
+ * Enable the peripheral devices on the IT8671F Super IO chip
+ */
+
+/* The base address is 0x3F0, 0x3bd or 0x370, depending on config bytes */
+
+#define SIO_BASE $0x3f0
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA  SIO_BASE+1
+
+#define SIO_READ(ldn, index) \
+	mov SIO_BASE, %dx	; \
+	mov $0x07, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	mov ldn, %al		; \
+	outb %al, %dx		; \
+	dec %dx			; \
+	mov index, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	inb %dx, %al		;
+
+#define SIO_WRITE(ldn, index, data) \
+	mov SIO_BASE, %dx	; \
+	mov $0x07, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	mov ldn, %al		; \
+	outb %al, %dx		; \
+	dec %dx			; \
+	mov index, %al		; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	mov data, %al		; \
+	outb %al, %dx		;
+
+
+	/* Perform MB PnP setup to put the SIO chip at 0x3f0 */
+
+	/* Base address 0x3f0 :	 0x86 0x80 0x55 0x55 */
+	/* Base address 0x3bd :	 0x86 0x80 0x55 0xaa */
+	/* Base address 0x370 :	 0x86 0x80 0xaa 0x55 */
+		
+	mov $0x279, %dx
+	mov $0x86, %al
+	outb %al, %dx
+	mov $0x80, %al
+	outb %al, %dx
+	mov $0x55, %al
+	outb %al, %dx
+	mov $0x55, %al
+	outb %al, %dx
+
+	/* Enter the configuration state */
+
+	mov SIO_BASE, %dx
+
+	/* 6a, b5, da, ed : f6, fb, 7d, be */
+
+	mov $0x6a, %al
+	outb %al, %dx
+	mov $0xb5, %al
+	outb %al, %dx
+	mov $0xda, %al
+	outb %al, %dx
+	mov $0xed, %al
+	outb %al, %dx
+
+	mov $0xf6, %al
+	outb %al, %dx
+	mov $0xfb, %al
+	outb %al, %dx
+	mov $0x7d, %al
+	outb %al, %dx
+	mov $0xbe, %al
+	outb %al, %dx
+			
+	/* df, 6f, 37, 1b : 0d, 86, c3, 61 */
+
+	mov $0xdf, %al
+	outb %al, %dx
+	mov $0x6f, %al
+	outb %al, %dx
+	mov $0x37, %al
+	outb %al, %dx
+	mov $0x1b, %al
+	outb %al, %dx
+
+	mov $0x0d, %al
+	outb %al, %dx
+	mov $0x86, %al
+	outb %al, %dx
+	mov $0xc3, %al
+	outb %al, %dx
+	mov $0x61, %al
+	outb %al, %dx
+			
+	/* b0, 58, 2c, 16 : 8b, 45, a2, d1 */
+
+	mov $0xb0, %al
+	outb %al, %dx
+	mov $0x58, %al
+	outb %al, %dx
+	mov $0x2c, %al
+	outb %al, %dx
+	mov $0x16, %al
+	outb %al, %dx
+
+	mov $0x8b, %al
+	outb %al, %dx
+	mov $0x45, %al
+	outb %al, %dx
+	mov $0xa2, %al
+	outb %al, %dx
+	mov $0xd1, %al
+	outb %al, %dx
+
+	/* e8, 74, 3a, 9d : ce, e7, 73, 39 */
+
+	mov $0xe8, %al
+	outb %al, %dx
+	mov $0x74, %al
+	outb %al, %dx
+	mov $0x3a, %al
+	outb %al, %dx
+	mov $0x9d, %al
+	outb %al, %dx
+
+	mov $0xce, %al
+	outb %al, %dx
+	mov $0xe7, %al
+	outb %al, %dx
+	mov $0x73, %al
+	outb %al, %dx
+	mov $0x39, %al
+	outb %al, %dx
+
+	/* Enable parallel port, serial 1, serial port 2, Floppy */
+	
+	SIO_WRITE($0x00, $0x23, $0x0f)
+
+	/* Activate serial port 1 and 2 */
+
+	SIO_WRITE($0x01, $0x30, $0x1)
+	SIO_WRITE($0x02, $0x30, $0x1)
+
+	/* Select 24MHz CLKIN and clear software suspend mode */
+	
+	SIO_WRITE($0x00, $0x24, $0x00)
+
+	/* Exit the configuration state */
+
+	SIO_WRITE($0x00, $0x02, $0x02);