From eee5be070a0561cdd6b030f9c8954f3010f68e88 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 17 Aug 2025 14:54:33 +0200 Subject: [PATCH] cpu/intel: Use mtrr_use_temp_range() Cover the SPIROM with a temporary MTRR to speed up SPI flash accesses after MPinit has removed the MTRR that was installed for postcar stage. TEST=Booted on Lenovo X220 and measured using cbmem -t: Before: 16:finished LZMA decompress (ignore for x86) 1,391,520 (366,351) After: 16:finished LZMA decompress (ignore for x86) 1,218,418 (210,054) Boots 156msec faster than before. Change-Id: Ia3df06b5c2a09e05c76361f3e38be83475122ee7 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/88811 Reviewed-by: Shuo Liu Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell_init.c | 4 ++++ src/cpu/intel/model_2065x/model_2065x_init.c | 4 ++++ src/cpu/intel/model_206ax/model_206ax_init.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 8232453a57..a54a01ad8f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -579,6 +579,10 @@ void mp_init_cpus(struct bus *cpu_bus) cpu_cluster = cpu_bus->dev; /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); + + /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(CACHE_ROM_BASE, CAR_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index cb74854346..70a2d1ae80 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -167,6 +167,10 @@ void mp_init_cpus(struct bus *cpu_bus) { /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); + + /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(CACHE_ROM_BASE, CAR_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 23310a303b..21a13f3d11 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -547,6 +547,10 @@ void mp_init_cpus(struct bus *cpu_bus) { /* TODO: Handle mp_init_with_smm failure? */ mp_init_with_smm(cpu_bus, &mp_ops); + + /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ + mtrr_use_temp_range(CACHE_ROM_BASE, CAR_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); } static struct device_operations cpu_dev_ops = {