From eed380e09075e1eef0bde7d1bb15c4343f30bfe0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 25 Oct 2013 04:25:42 -0700 Subject: [PATCH] tegra124: Fix the disp1 source field. This field was being set with the clock_ll_source_divisor function, but that doesn't use the right shift amount when setting the source, and the disp1 register doesn't have a divisor field. Also, because there's no divisor, we need to use a PLL that's already at the right frequency. Since PLLC is at 600MHz and is the PLL used for disp1 in U-Boot (according to the comment), lets use that instead of PLLD. BUG=None TEST=Built and booted into the kernel on nyan. Saw that it no longer tripped over its shoe laces when an illegal source was used for disp1. BRANCH=None Change-Id: Ibeeb6483bfedcaac994d78a0773fab41d982ae9c Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/174701 Reviewed-by: Hung-Te Lin Commit-Queue: Gabe Black Tested-by: Gabe Black Reviewed-by: Ronald Minnich --- src/soc/nvidia/tegra124/display.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index cdc10b2067..b7993008d5 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -285,11 +285,12 @@ void display_startup(device_t dev) clock_ll_set_source_divisor(&clk_rst->clk_src_host1x, 4, CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000)); - /* u-boot uses PLLC for DISP1. - * But the u-boot code does not work and we don't set up PLLC anyway. - * PLLP seems quite good enough, so run with that for now. */ - clock_ll_set_source_divisor(&clk_rst->clk_src_disp1, 0 /* 4 */, - CLK_DIVIDER(TEGRA_PLLP_KHZ, 600000)); + + /* DISP1 doesn't support a divisor. Use PLLC which runs at 600MHz. */ + val = readl(&clk_rst->clk_src_disp1); + val &= ~CLK_SOURCE3_MASK; + val |= (4 << CLK_SOURCE3_SHIFT); + writel(val, &clk_rst->clk_src_disp1); udelay(2);