From ee7c3ea182b35bb6ce3c62f301c4515714f6e654 Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Mon, 10 Mar 2014 14:46:06 -0700 Subject: [PATCH] libpayload: usb: xhci: Treat port reset as a port status change If a port is connected before and after an xhci controller reset, the PORTSC CSC bit may not be asserted. Add an additional check in xhci_rh_port_status_changed for the PRC bit so we can correctly handle ports in such a state. BUG=chrome-os-partner:24090 TEST=Manual on Rambi: - Boot Chromium OS from USB 3.0 drive - Issue 'reboot' on command line - Boot from USB 3.0 drive again successfully Also -- - Boot Chromium OS from USB 3.0 drive - Issue 'reboot' on command line - Boot Chromium OS from eMMC - Issue 'reboot' on command line - Boot from USB 3.0 drive again successfully Also, verify that USB ports continue to function correctly, and USB 3.0 device is always detected in Chromium OS as a superspeed device. BRANCH=Rambi Signed-off-by: Shawn Nematbakhsh Change-Id: I2d623aae647ab13711badd7211ab467afdc69548 Reviewed-on: https://chromium-review.googlesource.com/189394 Reviewed-by: Julius Werner --- payloads/libpayload/drivers/usb/xhci_rh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index 26bb4f9c02..fa118fe460 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -51,7 +51,7 @@ xhci_rh_port_status_changed(usbdev_t *const dev, const int port) xhci_t *const xhci = XHCI_INST(dev->controller); volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc; - const int changed = !!(*portsc & PORTSC_CSC); + const int changed = !!(*portsc & (PORTSC_CSC | PORTSC_PRC)); /* always clear all the status change bits */ *portsc = (*portsc & PORTSC_RW_MASK) | 0x00ef0000; return changed;