mb/google/fatcat/var/felino: Modify the overridetree file
Modify overridetree based on the schematics revision 20241120. BUG=b:379797598 TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino Change-Id: I40362b5c823144b6ab0acb878e58b4f5a295bbdd Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tongtong Pan
Subrata Banik
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1 changed files with 230 additions and 0 deletions
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@ -1,7 +1,237 @@
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fw_config
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field PDC_CONTROL 0 1
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option PDC_RTS 0
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option PDC_TI 1
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end
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field STORAGE 15 16
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option STORAGE_UNKNOWN 0
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option STORAGE_NVME_GEN4 1
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option STORAGE_NVME_GEN5 2
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option STORAGE_UFS 3
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end
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end
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chip soc/intel/pantherlake
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register "power_limits_config[PTL_U_1_CORE]" = "{
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.tdp_pl1_override = 15,
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.tdp_pl2_override = 25,
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}"
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register "power_limits_config[PTL_H_1_CORE]" = "{
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.tdp_pl1_override = 25,
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.tdp_pl2_override = 25,
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}"
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register "power_limits_config[PTL_H_2_CORE]" = "{
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.tdp_pl1_override = 25,
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.tdp_pl2_override = 25,
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}"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 # USB HUB (USB2 Camera)
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register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 /
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 /
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#gpe configuration
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register "pmc_gpe0_dw0" = "GPP_A"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_F"
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# Enable EDP in PortA
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register "ddi_port_A_config" = "1"
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register "ddi_ports_config" = "{
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[DDI_PORT_A] = DDI_ENABLE_HPD,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C1 | cr50 TPM. |
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#| I2C4 | CLICK PAD |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[1] = {
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.early_init=1,
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.speed = I2C_SPEED_FAST,
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},
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.i2c[4] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref igpu on end
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device ref ipu on end
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device ref iaa off end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(2, 2)"
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device ref tcss_usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C3""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(4, 2)"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(3, 2)"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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register "group" = "ACPI_PLD_GROUP(5, 1)"
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device ref usb2_port5 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port 1""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port 1""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(1, 2)"
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device ref usb3_port2 on end
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end
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end
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end
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end
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device ref tcss_dma1 on
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chip drivers/intel/usb4/retimer
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use tcss_usb3_port2 as dfp[0].typec_port
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device generic 0 on end
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end
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chip drivers/intel/usb4/retimer
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use tcss_usb3_port3 as dfp[1].typec_port
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device generic 0 on end
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end
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end
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device ref pcie_rp1 on
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# Enable PCH PCIE x1 slot using CLK 2
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register "pcie_rp[PCIE_RP(3)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "srcclk_pin" = "2"
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device generic 0 on end
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end
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end # SD Card
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device ref pcie_rp3 on
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register "pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 4,
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.clk_req = 4,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
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register "srcclk_pin" = "4"
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device pci 00.0 on end
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end
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chip drivers/wifi/generic
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register "add_acpi_dma_property" = "true"
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register "wake" = "GPE0_DW0_12" # GPP_A12
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use usb2_port7 as bluetooth_companion
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device pci 00.0 on end
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end
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end # WLAN
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device ref pcie_rp9 on
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register "pcie_rp[PCIE_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "is_storage" = "true"
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register "srcclk_pin" = "1"
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device generic 0 on end
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end
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end # Gen5 SSD
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device ref hda on
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chip drivers/intel/soundwire
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device generic 0 on
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chip drivers/soundwire/alc711
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# SoundWire Link 3 ID 1
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register "desc" = ""Headset Codec""
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device generic 3.1 on
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end
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end
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end
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end
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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register "add_acpi_dma_property" = "true"
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register "enable_cnvi_ddr_rfim" = "true"
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device generic 0 on end
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end
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end # CNVi
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device ref i2c0 on end
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device ref i2c1 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_F15_IRQ)"
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device i2c 50 on end
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end
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end # I2C1
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device ref i2c4 on
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chip drivers/i2c/hid
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register "generic.hid" = ""P3840""
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register "generic.desc" = ""Synaptics TOUCHPAD""
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register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E18_IRQ)"
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register "generic.uid" = "5"
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register "generic.detect" = "1"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
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end
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end # I2C4
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end
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end
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