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rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu

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Before, we calculate the pwm duties for cpu cores and centerlogic by
hand, adding pwm_regulator.c to handle this. The default pwm design
min/max voltage may be different between revs.

With the pwm regulator, this patch changes the little cpu frequency from
600M to 1512M, and raises CPU voltage to 1.2V correspondingly.

This also means we decide to drop the ES1 because it may fail to
bootup with 1.5G ~ 1.2v.

BRANCH=none
BUG=chrome-os-partner:54376,chrome-os-partner:54862
TEST=Bootup on kevin board

Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/364410
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Eric Gao 2016-07-29 12:34:32 +08:00 • committed by chrome-bot
commit ee4365c787
9 changed files with 140 additions and 73 deletions
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2
src/soc/rockchip/rk3399/Makefile.inc
View file

@ -23,10 +23,12 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
endif
bootblock-y += ../common/gpio.c
bootblock-y += ../common/pwm.c
bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += gpio.c
bootblock-y += mmu_operations.c
bootblock-y += saradc.c
bootblock-y += timer.c
verstage-y += ../common/cbmem.c

1
src/soc/rockchip/rk3399/bootblock.c
View file

@ -22,7 +22,6 @@
void bootblock_soc_init(void)
{
rkclk_init();
rkclk_configure_cpu(APLL_600_MHZ, false);
/* all ddr range non-secure */
write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);

6
src/soc/rockchip/rk3399/clock.c
View file

@ -47,11 +47,11 @@ static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
static const struct pll_div apll_1512_cfg = PLL_DIVISORS(1512*MHz, 1, 1, 1);
static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 3, 1);
static const struct pll_div *apll_cfgs[] = {
[APLL_1600_MHZ] = &apll_1600_cfg,
[APLL_1512_MHZ] = &apll_1512_cfg,
[APLL_600_MHZ] = &apll_600_cfg,
};

2
src/soc/rockchip/rk3399/include/soc/clock.h
View file

@ -97,7 +97,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
#define PWM_CLOCK_HZ PMU_PCLK_HZ
enum apll_frequencies {
APLL_1600_MHZ,
APLL_1512_MHZ,
APLL_600_MHZ,
};