From ee30558c49c9c4622277785ee0cd54c32720e489 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 12 Jan 2024 16:22:19 +0100 Subject: [PATCH] soc/intel/skylake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Signed-off-by: Nico Huber Signed-off-by: Nicholas Sudsgaard Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917 Reviewed-by: Erik van den Bogaert Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/devicetree.cb | 3 -- .../acer/aspire_vn7_572g/devicetree.cb | 4 --- src/mainboard/asrock/h110m/devicetree.cb | 3 -- .../clevo/kbl-u/variants/n13xwu/devicetree.cb | 4 --- .../dell/optiplex_3050/devicetree.cb | 3 -- src/mainboard/facebook/monolith/devicetree.cb | 3 -- src/mainboard/google/eve/devicetree.cb | 2 -- .../fizz/variants/baseboard/devicetree.cb | 6 ---- .../fizz/variants/endeavour/overridetree.cb | 15 ++-------- src/mainboard/google/glados/devicetree.cb | 1 - .../google/poppy/variants/atlas/devicetree.cb | 1 - .../poppy/variants/baseboard/devicetree.cb | 1 - .../google/poppy/variants/nami/devicetree.cb | 3 -- .../poppy/variants/nautilus/devicetree.cb | 1 - .../poppy/variants/nocturne/devicetree.cb | 2 -- .../poppy/variants/rammus/devicetree.cb | 1 - .../poppy/variants/soraka/devicetree.cb | 1 - src/mainboard/hp/280_g2/devicetree.cb | 4 --- .../kblrvp/variants/rvp11/overridetree.cb | 6 ---- .../kblrvp/variants/rvp3/overridetree.cb | 5 ---- .../kblrvp/variants/rvp7/overridetree.cb | 5 ---- .../kblrvp/variants/rvp8/overridetree.cb | 4 --- src/mainboard/intel/kunimitsu/devicetree.cb | 2 -- src/mainboard/intel/saddlebrook/devicetree.cb | 4 --- src/mainboard/kontron/bsl6/devicetree.cb | 12 ++------ .../bsl6/variants/bsl6/overridetree.cb | 25 ++++------------ src/mainboard/lenovo/m900/devicetree.cb | 3 -- src/mainboard/lenovo/m900_tiny/devicetree.cb | 2 -- .../lenovo/thinkcentre_m710s/devicetree.cb | 6 ---- src/mainboard/libretrend/lt1000/devicetree.cb | 10 +------ .../protectli/vault_kbl/devicetree.cb | 7 ----- src/mainboard/purism/librem_skl/devicetree.cb | 8 ++--- .../razer/blade_stealth_kbl/devicetree.cb | 3 -- .../starbook/variants/kbl/devicetree.cb | 2 -- .../variants/x11ssh-f/overridetree.cb | 7 ----- .../variants/x11ssh-tf/overridetree.cb | 4 --- .../variants/x11ssm-f/overridetree.cb | 5 ---- .../variants/x11ssw-f/overridetree.cb | 5 ---- src/mainboard/system76/kbl-u/devicetree.cb | 4 --- src/soc/intel/skylake/Makefile.mk | 2 ++ src/soc/intel/skylake/chip.c | 22 ++------------ src/soc/intel/skylake/chip.h | 7 ----- src/soc/intel/skylake/include/soc/pcie.h | 10 +++++++ src/soc/intel/skylake/pcie_rp.c | 29 +++++++++++++++++++ src/soc/intel/skylake/romstage/fsp_params.c | 11 ++----- 45 files changed, 60 insertions(+), 208 deletions(-) create mode 100644 src/soc/intel/skylake/include/soc/pcie.h create mode 100644 src/soc/intel/skylake/pcie_rp.c diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index a5bb944cb3..a2e08bf862 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -89,7 +89,6 @@ chip soc/intel/skylake end device ref pcie_rp3 on # Ethernet controller - register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpClkSrcNumber[2]" = "0" @@ -98,7 +97,6 @@ chip soc/intel/skylake end device ref pcie_rp4 on # Wireless controller - register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" @@ -107,7 +105,6 @@ chip soc/intel/skylake end device ref pcie_rp9 on # NVMe controller - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 60136ed84a..f308894c5b 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -251,7 +251,6 @@ chip soc/intel/skylake # Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text) device ref pcie_rp1 on # dGPU; x4 - register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" @@ -260,7 +259,6 @@ chip soc/intel/skylake end device ref pcie_rp7 on # NGFF; x2 - register "PcieRpEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" @@ -269,7 +267,6 @@ chip soc/intel/skylake end device ref pcie_rp9 on # LAN - register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" @@ -278,7 +275,6 @@ chip soc/intel/skylake end device ref pcie_rp10 on # WLAN - register "PcieRpEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" register "PcieRpLtrEnable[9]" = "true" register "PcieRpClkReqSupport[9]" = "1" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index cc36ce8ec7..9be53d7b7d 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -113,7 +113,6 @@ chip soc/intel/skylake end device ref pcie_rp1 on end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "2" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -122,7 +121,6 @@ chip soc/intel/skylake register "PcieRpHotPlug[4]" = "1" end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" # Disable CLKREQ#, since onboard LAN is always present register "PcieRpClkReqSupport[5]" = "0" @@ -131,7 +129,6 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "1" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "3" register "PcieRpAdvancedErrorReporting[6]" = "1" diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 15e7064131..54c59ddf40 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -66,7 +66,6 @@ chip soc/intel/skylake device ref uart2 on end device ref pcie_rp1 on device pci 00.0 on end # x4 TBT - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -76,7 +75,6 @@ chip soc/intel/skylake end device ref pcie_rp5 on device pci 00.0 on end # x1 LAN - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -84,7 +82,6 @@ chip soc/intel/skylake end device ref pcie_rp6 on device pci 00.0 on end # x1 WLAN - register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -93,7 +90,6 @@ chip soc/intel/skylake end device ref pcie_rp9 on device pci 00.0 on end # x4 M.2/M (J_SSD1) - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb index da11085ab6..0d2adff74a 100644 --- a/src/mainboard/dell/optiplex_3050/devicetree.cb +++ b/src/mainboard/dell/optiplex_3050/devicetree.cb @@ -39,7 +39,6 @@ chip soc/intel/skylake # M.2 SSD device ref pcie_rp21 on - register "PcieRpEnable[20]" = "1" register "PcieRpClkReqSupport[20]" = "1" register "PcieRpClkReqNumber[20]" = "3" register "PcieRpAdvancedErrorReporting[20]" = "1" @@ -50,14 +49,12 @@ chip soc/intel/skylake # Realtek LAN device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "0" register "PcieRpHotPlug[4]" = "0" end # M.2 WiFi device ref pcie_rp8 on - register "PcieRpEnable[7]" = "1" register "PcieRpClkReqSupport[7]" = "0" register "PcieRpHotPlug[7]" = "1" end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index d87db24114..6cacba505a 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -157,7 +157,6 @@ chip soc/intel/skylake device ref pcie_rp3 on # x1 baseboard WWAN # PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard - register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "0" register "PcieRpMaxPayload[2]" = "RpMaxPayload_256" register "PcieRpLtrEnable[2]" = "true" @@ -167,7 +166,6 @@ chip soc/intel/skylake device ref pcie_rp6 on # x1 baseboard i210 # PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard - register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "0" register "PcieRpMaxPayload[5]" = "RpMaxPayload_256" register "PcieRpLtrEnable[5]" = "true" @@ -177,7 +175,6 @@ chip soc/intel/skylake device ref pcie_rp9 on # x4 FPGA # PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpHotPlug[8]" = "1" register "PcieRpMaxPayload[8]" = "RpMaxPayload_256" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 5ff43927a5..15e2ff6095 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -336,7 +336,6 @@ chip soc/intel/skylake end end # I2C #4 device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" @@ -349,7 +348,6 @@ chip soc/intel/skylake end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" register "PcieRpAdvancedErrorReporting[4]" = "1" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index d2bb08e830..8cf8d27da6 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -289,7 +289,6 @@ chip soc/intel/skylake device ref pcie_rp3 on # LAN, will be swapped to port 1 by FSP # x1 - register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "0" register "PcieRpAdvancedErrorReporting[2]" = "1" @@ -304,7 +303,6 @@ chip soc/intel/skylake end device ref pcie_rp4 on # x1 WLAN - register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "5" register "PcieRpAdvancedErrorReporting[3]" = "1" @@ -317,7 +315,6 @@ chip soc/intel/skylake end device ref pcie_rp5 on # x4 NVMe - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -326,7 +323,6 @@ chip soc/intel/skylake end device ref pcie_rp9 on # 2nd LAN - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpAdvancedErrorReporting[8]" = "1" @@ -339,7 +335,6 @@ chip soc/intel/skylake end end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "true" register "PcieRpClkReqSupport[10]" = "1" register "PcieRpClkReqNumber[10]" = "2" register "PcieRpAdvancedErrorReporting[10]" = "1" @@ -347,7 +342,6 @@ chip soc/intel/skylake register "PcieRpClkSrcNumber[10]" = "2" end device ref pcie_rp12 on - register "PcieRpEnable[11]" = "true" register "PcieRpClkReqSupport[11]" = "1" register "PcieRpClkReqNumber[11]" = "2" register "PcieRpAdvancedErrorReporting[11]" = "1" diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 7b6de183e7..8421ae477e 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -116,7 +116,6 @@ chip soc/intel/skylake end device ref pcie_rp7 on # x1 TPU1 - register "PcieRpEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "4" register "PcieRpAdvancedErrorReporting[6]" = "1" @@ -125,7 +124,6 @@ chip soc/intel/skylake end device ref pcie_rp8 on # x1 TPU0 - register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "2" register "PcieRpAdvancedErrorReporting[7]" = "1" @@ -134,20 +132,13 @@ chip soc/intel/skylake end device ref pcie_rp9 on # x4 i350 LAN - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "0" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "2" end - device ref pcie_rp10 off - register "PcieRpEnable[9]" = "false" - end - device ref pcie_rp11 off - register "PcieRpEnable[10]" = "false" - end - device ref pcie_rp12 off - register "PcieRpEnable[11]" = "false" - end + device ref pcie_rp10 off end + device ref pcie_rp11 off end + device ref pcie_rp12 off end end end diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index bac1ed3cc0..5bbcd2cf17 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -78,7 +78,6 @@ chip soc/intel/skylake device ref uart2 on end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d1a3542dc3..0ef59f8a91 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -310,7 +310,6 @@ chip soc/intel/skylake end device ref pcie_rp1 on # WLAN - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 160dfd333e..5bc4bdce00 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -323,7 +323,6 @@ chip soc/intel/skylake end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index e32e5e4557..2e7726ec1d 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -366,7 +366,6 @@ chip soc/intel/skylake device ref pcie_rp1 on end device ref pcie_rp4 on # x1 - register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" @@ -379,7 +378,6 @@ chip soc/intel/skylake end device ref pcie_rp5 on # x4 - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -388,7 +386,6 @@ chip soc/intel/skylake end device ref pcie_rp9 on # x2 - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index dfb11ee48c..b226e6b6a6 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -361,7 +361,6 @@ chip soc/intel/skylake end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index e64d408eb2..fd95a61b45 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -325,7 +325,6 @@ chip soc/intel/skylake end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" @@ -338,7 +337,6 @@ chip soc/intel/skylake end device ref pcie_rp9 on # x2 - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 3251916ffc..a84e45748c 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -314,7 +314,6 @@ chip soc/intel/skylake end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 7602bcb6bf..29d6974bc1 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -305,7 +305,6 @@ chip soc/intel/skylake end device ref i2c4 on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index afb564ece5..4c17d5de48 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -64,14 +64,12 @@ chip soc/intel/skylake device ref uart2 on end device ref pcie_rp5 on # IT8893E PCI Bridge - register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpClkSrcNumber[4]" = "11" end device ref pcie_rp6 on # PCIe x1 slot - register "PcieRpEnable[5]" = "1" register "PcieRpHotPlug[5]" = "1" register "PcieRpLtrEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" @@ -79,14 +77,12 @@ chip soc/intel/skylake end device ref pcie_rp7 on # RTL8111 GbE NIC - register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "true" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpClkSrcNumber[6]" = "10" end device ref pcie_rp8 on # M.2 2230 slot - register "PcieRpEnable[7]" = "1" register "PcieRpHotPlug[7]" = "1" register "PcieRpLtrEnable[7]" = "true" register "PcieRpAdvancedErrorReporting[7]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 5da43c2098..cc3d9555be 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -75,37 +75,31 @@ chip soc/intel/skylake end device ref i2c4 off end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "1" register "PcieRpClkReqNumber[6]" = "2" register "PcieRpClkSrcNumber[6]" = "2" end device ref pcie_rp8 on - register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" register "PcieRpClkSrcNumber[7]" = "3" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" register "PcieRpClkSrcNumber[8]" = "4" end device ref pcie_rp14 on - register "PcieRpEnable[13]" = "true" register "PcieRpClkReqSupport[13]" = "1" register "PcieRpClkReqNumber[13]" = "5" register "PcieRpClkSrcNumber[13]" = "5" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "true" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" register "PcieRpClkSrcNumber[16]" = "7" diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 1880cd9fa9..93e62e2776 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -77,35 +77,30 @@ chip soc/intel/skylake device ref cio on end device ref pcie_rp1 on # PCIE x4 -> SLOT1 - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "2" register "PcieRpClkSrcNumber[0]" = "2" end device ref pcie_rp5 on # PCIE x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on # PCIE x1 -> SLOT3 - register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "1" register "PcieRpClkSrcNumber[5]" = "1" end device ref pcie_rp9 on # PCIE x1 -> WLAN - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" end device ref pcie_rp10 on # PCIE x1 -> WiGig - register "PcieRpEnable[9]" = "true" register "PcieRpClkReqSupport[9]" = "1" register "PcieRpClkReqNumber[9]" = "4" register "PcieRpClkSrcNumber[9]" = "4" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index a030fe758f..a5d30d3640 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -124,31 +124,26 @@ chip soc/intel/skylake }" end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "true" register "PcieRpClkReqSupport[2]" = "1" register "PcieRpClkReqNumber[2]" = "5" register "PcieRpClkSrcNumber[2]" = "5" end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "2" register "PcieRpClkSrcNumber[3]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "1" register "PcieRpClkSrcNumber[8]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 1b8e39124f..2d8a9c1263 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -148,22 +148,18 @@ chip soc/intel/skylake device ref pcie_rp1 off end device ref pcie_rp3 on end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "true" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "2" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "1" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "6" end device ref pcie_rp17 on - register "PcieRpEnable[16]" = "true" register "PcieRpClkReqSupport[16]" = "1" register "PcieRpClkReqNumber[16]" = "7" end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 758b913c98..c52b290d93 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -210,7 +210,6 @@ chip soc/intel/skylake end end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" chip drivers/wifi/generic @@ -219,7 +218,6 @@ chip soc/intel/skylake end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "2" end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index fd2ae4108b..b6000910e7 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -186,24 +186,20 @@ chip soc/intel/skylake device ref i2c4 on end device ref pcie_rp1 on end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "0" end device ref pcie_rp8 on # x1 - register "PcieRpEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "1" register "PcieRpClkReqNumber[7]" = "3" end device ref pcie_rp9 on # x4 - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "4" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "true" register "PcieRpClkReqSupport[12]" = "1" register "PcieRpClkReqNumber[12]" = "1" end diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 9fb142971f..26f31e026e 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -85,15 +85,9 @@ chip soc/intel/skylake [2] = 1, }" end - device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" - end - device ref pcie_rp10 on - register "PcieRpEnable[9]" = "true" - end - device ref pcie_rp11 on - register "PcieRpEnable[10]" = "true" - end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end device ref lpc_espi on register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index 5624d6bf38..2fa0145d75 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -20,26 +20,11 @@ chip soc/intel/skylake device ref sata on register "SataPortsEnable[3]" = "1" end - device ref pcie_rp1 on - # COMe 4 - register "PcieRpEnable[0]" = "true" - end - device ref pcie_rp2 on - # COMe 5 - register "PcieRpEnable[1]" = "true" - end - device ref pcie_rp3 on - # COMe 6 - register "PcieRpEnable[2]" = "true" - end - device ref pcie_rp4 on - # COMe 7 - register "PcieRpEnable[3]" = "true" - end - device ref pcie_rp12 on - # COMe 3 - register "PcieRpEnable[11]" = "true" - end + device ref pcie_rp1 on end # COMe 4 + device ref pcie_rp2 on end # COMe 5 + device ref pcie_rp3 on end # COMe 6 + device ref pcie_rp4 on end # COMe 7 + device ref pcie_rp12 on end # COMe 3 device ref smbus on chip drivers/i2c/nct7802y register "peci[0]" = "{ PECI_DOMAIN_0, 100 }" diff --git a/src/mainboard/lenovo/m900/devicetree.cb b/src/mainboard/lenovo/m900/devicetree.cb index 4f96ac186e..8b550a74d3 100644 --- a/src/mainboard/lenovo/m900/devicetree.cb +++ b/src/mainboard/lenovo/m900/devicetree.cb @@ -85,7 +85,6 @@ chip soc/intel/skylake }" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "false" register "PcieRpAdvancedErrorReporting[4]" = "true" register "PcieRpLtrEnable[4]" = "true" @@ -96,7 +95,6 @@ chip soc/intel/skylake "PCIE1X_1" "SlotDataBusWidth1X" end device ref pcie_rp7 on # M.2 E-key - register "PcieRpEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "true" register "PcieRpClkReqNumber[6]" = "4" register "PcieRpAdvancedErrorReporting[6]" = "true" @@ -108,7 +106,6 @@ chip soc/intel/skylake "M_2" "SlotDataBusWidth1X" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "false" register "PcieRpAdvancedErrorReporting[8]" = "true" register "PcieRpLtrEnable[8]" = "true" diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index 88245c3c1d..439cbc1ebc 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -161,14 +161,12 @@ chip soc/intel/skylake }" end device ref pcie_rp17 on # M.2 2280 / 2242 - SSD - register "PcieRpEnable[16]" = "1" register "PcieRpAdvancedErrorReporting[16]" = "1" register "PcieRpLtrEnable[16]" = "true" register "PcieRpClkSrcNumber[16]" = "7" register "PcieRpHotPlug[16]" = "1" end device ref pcie_rp7 on # M.2 2230 - WLAN - register "PcieRpEnable[6]" = "1" register "PcieRpAdvancedErrorReporting[6]" = "1" register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkSrcNumber[6]" = "1" diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb index 4d1828c5ab..04e6e7d672 100644 --- a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb @@ -160,7 +160,6 @@ chip soc/intel/skylake }" end device ref pcie_rp5 on # USB_LAN - register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "true" register "PcieRpClkReqNumber[4]" = "5" @@ -173,7 +172,6 @@ chip soc/intel/skylake "PCIE1X_2" "SlotDataBusWidth1X" - register "PcieRpEnable[6]" = "true" register "PcieRpLtrEnable[6]" = "true" register "PcieRpClkReqSupport[6]" = "true" register "PcieRpClkReqNumber[6]" = "7" @@ -186,8 +184,6 @@ chip soc/intel/skylake "PCIE1X_1" "SlotDataBusWidth1X" - register "PcieRpEnable[7]" = "true" - register "PcieRpLtrEnable[7]" = "true" register "PcieRpClkReqSupport[7]" = "true" register "PcieRpClkReqNumber[7]" = "8" register "PcieRpClkSrcNumber[7]" = "8" @@ -199,7 +195,6 @@ chip soc/intel/skylake "M2_WIFI" "SlotDataBusWidth1X" - register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "true" register "PcieRpClkReqSupport[10]" = "true" register "PcieRpClkReqNumber[10]" = "1" @@ -212,7 +207,6 @@ chip soc/intel/skylake "M2_SSD" "SlotDataBusWidth1X" - register "PcieRpEnable[20]" = "true" register "PcieRpLtrEnable[20]" = "true" register "PcieRpClkReqSupport[20]" = "true" register "PcieRpClkReqNumber[20]" = "6" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 29d82de222..b503ad83eb 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -140,36 +140,28 @@ chip soc/intel/skylake }" register "SataSpeedLimit" = "2" end - device ref pcie_rp3 on - register "PcieRpEnable[2]" = "1" - end + device ref pcie_rp3 on end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "1" register "PcieRpClkSrcNumber[4]" = "2" smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" end device ref pcie_rp6 on end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" register "PcieRpClkSrcNumber[8]" = "3" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "SSD_M.2 2242/2280" "SlotDataBusWidth4X" end device ref pcie_rp10 on - register "PcieRpEnable[9]" = "1" register "PcieRpClkSrcNumber[9]" = "3" end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "true" register "PcieRpClkSrcNumber[10]" = "3" end device ref pcie_rp12 on - register "PcieRpEnable[11]" = "true" register "PcieRpClkSrcNumber[11]" = "3" end device ref lpc_espi on diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 30152b5462..b47c53c7b5 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -142,49 +142,42 @@ chip soc/intel/skylake end device ref pcie_rp1 on # LAN - register "PcieRpEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "true" register "PcieRpClkSrcNumber[0]" = "0" end device ref pcie_rp2 on # LAN - register "PcieRpEnable[1]" = "true" register "PcieRpAdvancedErrorReporting[1]" = "1" register "PcieRpLtrEnable[1]" = "true" register "PcieRpClkSrcNumber[1]" = "1" end device ref pcie_rp3 on # LAN - register "PcieRpEnable[2]" = "true" register "PcieRpAdvancedErrorReporting[2]" = "1" register "PcieRpLtrEnable[2]" = "true" register "PcieRpClkSrcNumber[2]" = "2" end device ref pcie_rp4 on # LAN - register "PcieRpEnable[3]" = "true" register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "true" register "PcieRpClkSrcNumber[3]" = "3" end device ref pcie_rp5 on # LAN - register "PcieRpEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "true" register "PcieRpClkSrcNumber[4]" = "4" end device ref pcie_rp6 on # LAN - register "PcieRpEnable[5]" = "true" register "PcieRpAdvancedErrorReporting[5]" = "1" register "PcieRpLtrEnable[5]" = "true" register "PcieRpClkSrcNumber[5]" = "5" end device ref pcie_rp9 on # mPCIe WIFI - register "PcieRpEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "true" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 9af8046762..67330b444b 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -143,12 +143,8 @@ chip soc/intel/skylake [2] = 1, }" end - device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" - end - device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" - end + device ref pcie_rp5 on end + device ref pcie_rp9 on end device ref lpc_espi on # EC/KBC requires continuous mode register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 637427adb5..55888fa02e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -157,16 +157,13 @@ chip soc/intel/skylake device ref uart2 on end device ref pcie_rp1 on end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "true" register "PcieRpLtrEnable[2]" = "true" end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "true" register "PcieRpHotPlug[4]" = "1" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "true" end device ref lpc_espi on diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index a9ac9c1554..0f1c922acd 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -89,7 +89,6 @@ chip soc/intel/skylake end device ref uart2 on end device ref pcie_rp6 on - register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "4" register "PcieRpClkSrcNumber[5]" = "4" @@ -101,7 +100,6 @@ chip soc/intel/skylake end end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "0" register "PcieRpClkSrcNumber[8]" = "0" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 15d217b2a5..0e431dc548 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -49,34 +49,27 @@ chip soc/intel/skylake end device ref igpu on end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp4 on - register "PcieRpEnable[3]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" end device ref pcie_rp7 on - register "PcieRpEnable[6]" = "true" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end device ref pcie_rp9 on # Slot JPCIE1 - register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 14dbb0fe84..7b38e10e6c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -41,12 +41,10 @@ chip soc/intel/skylake device ref peg0 on end # unused device ref peg1 on # Slot JPCIE1 - register "PcieRpEnable[0]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end device ref pcie_rp1 on # Slot JPCIE1 - register "PcieRpEnable[2]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end device ref pcie_rp3 on @@ -55,12 +53,10 @@ chip soc/intel/skylake end end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index d7505ef261..858297d6f1 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -44,20 +44,17 @@ chip soc/intel/skylake end device ref pcie_rp1 on # Slot JPCIE4 - register "PcieRpEnable[0]" = "true" register "PcieRpLtrEnable[0]" = "true" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp5 on # Slot JPCIE5 - register "PcieRpEnable[4]" = "true" register "PcieRpLtrEnable[4]" = "true" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp9 on - register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "true" register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 @@ -65,7 +62,6 @@ chip soc/intel/skylake end end device ref pcie_rp10 on - register "PcieRpEnable[9]" = "true" register "PcieRpLtrEnable[9]" = "true" register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 @@ -73,7 +69,6 @@ chip soc/intel/skylake end end device ref pcie_rp11 on - register "PcieRpEnable[10]" = "true" register "PcieRpLtrEnable[10]" = "true" register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index eec01fb73d..698cde3163 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -45,24 +45,19 @@ chip soc/intel/skylake smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" end device ref pcie_rp1 on - register "PcieRpEnable[0]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp2 on - register "PcieRpEnable[1]" = "true" device pci 00.0 on end # GbE end device ref pcie_rp5 on - register "PcieRpEnable[4]" = "true" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device ref pcie_rp9 on # Slot JSXB2 - register "PcieRpEnable[8]" = "true" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device ref pcie_rp13 on - register "PcieRpEnable[12]" = "true" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 10a5750ecc..4f3e148944 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -133,7 +133,6 @@ chip soc/intel/skylake end device ref pcie_rp1 on # Root port #1 x4 (TBT) - register "PcieRpEnable[0]" = "true" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "4" register "PcieRpClkSrcNumber[0]" = "4" @@ -143,7 +142,6 @@ chip soc/intel/skylake end device ref pcie_rp5 on # Root port #5 x1 (LAN) - register "PcieRpEnable[4]" = "true" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" @@ -152,7 +150,6 @@ chip soc/intel/skylake end device ref pcie_rp6 on # Root port #6 x1 (WLAN) - register "PcieRpEnable[5]" = "true" register "PcieRpClkReqSupport[5]" = "1" register "PcieRpClkReqNumber[5]" = "2" register "PcieRpClkSrcNumber[5]" = "2" @@ -161,7 +158,6 @@ chip soc/intel/skylake end device ref pcie_rp9 on # Root port #9 x4 (NVMe) - register "PcieRpEnable[8]" = "true" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "5" register "PcieRpClkSrcNumber[8]" = "5" diff --git a/src/soc/intel/skylake/Makefile.mk b/src/soc/intel/skylake/Makefile.mk index 6b082ed29e..04ba96b7dd 100644 --- a/src/soc/intel/skylake/Makefile.mk +++ b/src/soc/intel/skylake/Makefile.mk @@ -30,6 +30,7 @@ romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c romstage-y += me.c +romstage-y += pcie_rp.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -50,6 +51,7 @@ ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c ramstage-y += p2sb.c +ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-y += reset.c diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d7364fdca2..715c008666 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -34,22 +35,6 @@ #include "chip.h" -static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, - { 0 } -}; - -static const struct pcie_rp_group pch_h_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, - /* Sunrise Point PCH-H actually only has 4 ports in the - third group. But that would require a runtime check - and probing 4 non-existent ports shouldn't hurt. */ - { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -181,10 +166,7 @@ void soc_init_pre_device(void *chip_info) itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); /* swap enabled PCI ports in device tree if needed */ - if (CONFIG(SKYLAKE_SOC_PCH_H)) - pcie_rp_update_devicetree(pch_h_rp_groups); - else - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); } struct device_operations pci_domain_ops = { diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8d5a9d1414..d12c3eb218 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -170,13 +170,6 @@ struct soc_intel_skylake_config { Peg2_x2, } Peg2MaxLinkWidth; - /* - * Enable/Disable Root Port - * 0: Disable Root Port - * 1: Enable Root Port - */ - bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* * Enable/Disable Clk-req support for Root Port * 0: Disable Clk-Req diff --git a/src/soc/intel/skylake/include/soc/pcie.h b/src/soc/intel/skylake/include/soc/pcie.h new file mode 100644 index 0000000000..4c0713156f --- /dev/null +++ b/src/soc/intel/skylake/include/soc/pcie.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_SKYLAKE_PCIE_H__ +#define __SOC_SKYLAKE_PCIE_H__ + +#include + +const struct pcie_rp_group *get_pch_pcie_rp_table(void); + +#endif /* __SOC_SKYLAKE_PCIE_H__ */ diff --git a/src/soc/intel/skylake/pcie_rp.c b/src/soc/intel/skylake/pcie_rp.c new file mode 100644 index 0000000000..08e9c300dc --- /dev/null +++ b/src/soc/intel/skylake/pcie_rp.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pcie_rp_group pch_lp_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, + { 0 } +}; + +static const struct pcie_rp_group pch_h_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + /* Sunrise Point PCH-H actually only has 4 ports in the + third group. But that would require a runtime check + and probing 4 non-existent ports shouldn't hurt. */ + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, + { 0 } +}; + +const struct pcie_rp_group *get_pch_pcie_rp_table(void) +{ + if (CONFIG(SKYLAKE_SOC_PCH_H)) + return pch_h_rp_groups; + + return pch_lp_rp_groups; +} diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index bd3d086879..99bb5f1b6c 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -4,10 +4,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -75,9 +77,6 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { - int i; - uint32_t mask = 0; - m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; @@ -92,11 +91,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->DdrFreqLimit = 0; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->PrmrrSize = get_valid_prmrr_size(); - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1<PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); cpu_flex_override(m_cfg);