From ed1aa558ff3e857aa6bc282237a1e63b88647c31 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 1 Jun 2017 20:08:48 +0800 Subject: [PATCH] UPSTREAM: mb/google/fizz: set SD_CDZ to edge trigger. This is to align with the SD_CD GpioInt setting in acpi BUG=b:62067569 TEST=checked unused interrupt on SD_CD does not happen after s3 resume Change-Id: Id2c151cb8549e0c447c4a1494556f1cf6a55d0ac Signed-off-by: Patrick Georgi Original-Commit-Id: 8cb70914cab728ea01f5200d9d90dcb444d14f26 Original-Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a Original-Signed-off-by: Kane Chen Original-Reviewed-on: https://review.coreboot.org/20001 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Furquan Shaikh Reviewed-on: https://chromium-review.googlesource.com/523975 --- src/mainboard/google/fizz/gpio.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index 07d9281e75..ced33e97b0 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -42,7 +42,8 @@ static const struct pad_config gpio_table[] = { /* ESPI_IO3 */ /* ESPI_CS# */ /* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ -/* PIRQA# */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* SD_CDZ */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, + EDGE), /* SD_CDZ */ /* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ /* ESPI_CLK */ /* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */