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UPSTREAM: nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfaces

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Previously the ME PCI interface (HECI) was being reported as present in
the DMAR ACPI table even when ME firmware was missing or the PCI device
was hidden and HECI would be unresponsive.
Now we check via the PCI config space itself to verify if the HECI
is present or not.

Note that this test could fail if ME firmware is present but
HECI is disabled in devicetree, because it would not advertise that the HECI
exists even though there is a running ME.  Perhaps this behaviour is desirable
because in this case you won't see the HECI in the lspci tree anyway.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16330
Tested-by: build bot (Jenkins)
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0
Reviewed-on: https://chromium-review.googlesource.com/383694
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Damien Zammit 2016-08-27 00:35:48 +10:00 • committed by chrome-bot
commit ecb4adba5d
2 changed files with 4 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/northbridge/intel/gm45/acpi.c
View file

@ -72,7 +72,8 @@ unsigned long acpi_fill_mcfg(unsigned long current)
static unsigned long acpi_fill_dmar(unsigned long current)
{
int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL);
int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) &&
(pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff);
int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION);
unsigned long tmp = current;

2
src/northbridge/intel/gm45/iommu.c
View file

@ -40,6 +40,8 @@ void init_iommu()
}
if (me_active) {
MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */
} else {
MCHBAR32(0x10) = 0; /* disable IOMMU for ME */
}
MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */