erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: soc/apollolake: Add ish_enable in soc_intel_apollolake_config

Browse source 
Also initialize IshEnable in Silicon Init UPD with the value from
devicetree.cb

BUG=None
BRANCH=None
TEST=None

Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I8f57a7353471cc3efa21c7011cdd0b369d25275d
Original-Reviewed-on: https://review.coreboot.org/14894
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347455
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Hannah Williams 2016-03-28 14:45:59 -07:00 • committed by chrome-bot
commit ec164cf54f
2 changed files with 5 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/apollolake/chip.c
View file

@ -120,6 +120,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
/* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
silconfig->PmcBase = PMC_BAR0 + 0x1000;
silconfig->P2sbBase = P2SB_BAR;
silconfig->IshEnable = cfg->integrated_sensor_hub_enable;
}
struct chip_operations soc_intel_apollolake_ops = {

3
src/soc/intel/apollolake/chip.h
View file

@ -42,6 +42,9 @@ struct soc_intel_apollolake_config {
/* Configure serial IRQ (SERIRQ) line. */
enum serirq_mode serirq_mode;
/* Integrated Sensor Hub */
uint8_t integrated_sensor_hub_enable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */