soc/intel/tgl: Hook up ucode for TGL-U and TGL-R

Hook up microcode from 3rdparty repo for:

- TGL-U: 06-8c-01 (CPUID signature: 0x806c1)
- TGL-R: 06-8c-02 (CPUID signature: 0x806c2)

Verified microcode blob was found in CBFS on system76/darp7 (TGL-U).

    CBFS: Found 'cpu_microcode_blob.bin' @0x103c0 size 0x31c00 in mcache @0x76c2d0ac
    microcode: sig=0x806c1 pf=0x80 revision=0x88

coreboot reports the correct revision for the microcode.

Change-Id: I210c0133dad7ade63b9f7177aaa9a69b019469af
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56862
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/tigerlake/Kconfig

@@ -34,7 +34,6 @@ config CPU_SPECIFIC_OPTIONS
 	select MP_SERVICES_PPI_V1
 	select MRC_SETTINGS_PROTECT
 	select PARALLEL_MP_AP_WORK
-	select MICROCODE_BLOB_UNDISCLOSED
 	select PLATFORM_USES_FSP2_2
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK

src/soc/intel/tigerlake/Makefile.inc

@@ -58,4 +58,7 @@ verstage-y += gpio.c
 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
 CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
 
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-01
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8c-02
+
 endif