rk3399: clean up sdram controller initialization code
This is a purely cosmetic change replacing some of the more prominent
copy and paste sections of the code with compressed versions of the
same.
BRANCH=none
BUG=none
TEST=with the rest of the patches applied stressapptest still runs for
an hour on both Kevin and Gru.
Change-Id: I362e0e261209ae4d4890ecb0e08bb1956c172ffd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353774
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
This commit is contained in:
Vadim Bendebury
chrome-bot
parent
9de93beae0
commit
eb8043f964
1 changed files with 87 additions and 147 deletions
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@ -210,6 +210,7 @@ static void set_ds_odt(u32 channel,
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u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
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u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
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u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
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u32 reg_value;
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if (sdram_params->dramtype == LPDDR4) {
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tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
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@ -250,86 +251,43 @@ static void set_ds_odt(u32 channel,
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* sets termination values for read/idle cycles and drive strength
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* for write cycles for DQ/DM
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*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[6], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[134], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[262], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[390], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[6], 0xffffff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[134], 0xffffff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[262], 0xffffff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[390], 0xffffff, reg_value);
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/*
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* phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
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* sets termination values for read/idle cycles and drive strength
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* for write cycles for DQS
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*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[7], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[135], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[263], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[391], 0xffffff,
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tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
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(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
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(tsel_idle_select_n << 16) |
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(tsel_idle_select_p << 20));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[7], 0xffffff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[135], 0xffffff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[263], 0xffffff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[391], 0xffffff, reg_value);
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/*phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[544], 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[672], 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[800], 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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reg_value = tsel_wr_select_n | (tsel_wr_select_p << 0x4);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[544], 0xff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[672], 0xff, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[800], 0xff, reg_value);
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/*phy_pad_addr_drive 29bits DENALI_PHY_928 offset_0*/
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clrsetbits_le32((&ddr_publ_regs->denali_phy[928]), 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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clrsetbits_le32((&ddr_publ_regs->denali_phy[928]), 0xff, reg_value);
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/*phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[937], 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[937], 0xff, reg_value);
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/*phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[935], 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[935], 0xff, reg_value);
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/*phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0xff, reg_value);
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/*phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[929], 0xff,
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tsel_wr_select_n | (tsel_wr_select_p << 0x4));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[929], 0xff, reg_value);
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/*phy_pad_fdbk_drive 23bit DENALI_PHY_924/925*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[924], 0xff,
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@ -338,57 +296,41 @@ static void set_ds_odt(u32 channel,
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tsel_rd_select_n | (tsel_rd_select_p << 4));
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/* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
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clrsetbits_le32(&ddr_publ_regs->denali_phy[5], 0x7 << 16,
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(tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 16);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[133], 0x7 << 16,
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(tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 16);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[261], 0x7 << 16,
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(tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 16);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[389], 0x7 << 16,
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(tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) << 16);
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reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
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<< 16;
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clrsetbits_le32(&ddr_publ_regs->denali_phy[5], 0x7 << 16, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[133], 0x7 << 16, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[261], 0x7 << 16, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[389], 0x7 << 16, reg_value);
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/* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
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clrsetbits_le32(&ddr_publ_regs->denali_phy[6], 0x7 << 24,
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(tsel_rd_en | (tsel_wr_en << 1) |
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(tsel_idle_en << 2)) << 24);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[134], 0x7 << 24,
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(tsel_rd_en | (tsel_wr_en << 1) |
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(tsel_idle_en << 2)) << 24);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[262], 0x7 << 24,
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(tsel_rd_en | (tsel_wr_en << 1) |
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(tsel_idle_en << 2)) << 24);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[390], 0x7 << 24,
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(tsel_rd_en | (tsel_wr_en << 1) |
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(tsel_idle_en << 2)) << 24);
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reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
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<< 24;
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clrsetbits_le32(&ddr_publ_regs->denali_phy[6], 0x7 << 24, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[134], 0x7 << 24, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[262], 0x7 << 24, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[390], 0x7 << 24, reg_value);
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/* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
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clrsetbits_le32(&ddr_publ_regs->denali_phy[518],
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0x1 << 8, tsel_wr_en << 8);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[646],
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0x1 << 8, tsel_wr_en << 8);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[774],
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0x1 << 8, tsel_wr_en << 8);
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reg_value = tsel_wr_en << 8;
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clrsetbits_le32(&ddr_publ_regs->denali_phy[518], 0x1 << 8, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[646], 0x1 << 8, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[774], 0x1 << 8, reg_value);
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/* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
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clrsetbits_le32((&ddr_publ_regs->denali_phy[933]),
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0x1 << 17, tsel_wr_en << 17);
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reg_value = tsel_wr_en << 17;
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clrsetbits_le32((&ddr_publ_regs->denali_phy[933]), 0x1 << 17,
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reg_value);
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/*
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* pad_rst/cke/cs/clk_term tsel 1bits
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* DENALI_PHY_938/936/940/934 offset_17
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*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[938],
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0x1 << 17, tsel_wr_en << 17);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[936],
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0x1 << 17, tsel_wr_en << 17);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[940],
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0x1 << 17, tsel_wr_en << 17);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[934],
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0x1 << 17, tsel_wr_en << 17);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[938], 0x1 << 17, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[936], 0x1 << 17, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[940], 0x1 << 17, reg_value);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[934], 0x1 << 17, reg_value);
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/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
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clrsetbits_le32(&ddr_publ_regs->denali_phy[930],
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0x1 << 17, tsel_wr_en << 17);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[930], 0x1 << 17, reg_value);
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}
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static void phy_io_config(u32 channel,
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@ -398,6 +340,7 @@ static void phy_io_config(u32 channel,
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u32 vref_mode, vref_value;
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u32 mode_sel;
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u32 speed;
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u32 reg_value;
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/*vref setting*/
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if (sdram_params->dramtype == LPDDR4)
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@ -408,23 +351,20 @@ static void phy_io_config(u32 channel,
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vref_mode = 0x1;
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vref_value = 0x1f;
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reg_value = (vref_mode << 9) | (0x1 << 8) | vref_value;
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/*PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[913],
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0xfff << 8, ((vref_mode<<9)|(0x1<<8)|vref_value) << 8);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[913], 0xfff << 8,
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reg_value << 8);
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/*PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[914],
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0xfff, ((vref_mode<<9)|(0x1<<8)|vref_value));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[914], 0xfff, reg_value);
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/*PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[914],
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0xfff << 16, ((vref_mode<<9)|(0x1<<8)|vref_value)
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<< 16);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[914], 0xfff << 16,
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reg_value << 16);
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/*PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[915],
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0xfff, ((vref_mode<<9)|(0x1<<8)|vref_value));
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clrsetbits_le32(&ddr_publ_regs->denali_phy[915], 0xfff, reg_value);
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/*PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[915],
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0xfff << 16, ((vref_mode<<9)|(0x1<<8)|vref_value)
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<< 16);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[915], 0xfff << 16,
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reg_value << 16);
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/*mode setting*/
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if (sdram_params->dramtype == LPDDR4)
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@ -437,29 +377,29 @@ static void phy_io_config(u32 channel,
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mode_sel = 0x1;
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/*PHY_924 PHY_PAD_FDBK_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[924],
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0x7 << 15, mode_sel << 15);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[924], 0x7 << 15,
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mode_sel << 15);
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/*PHY_926 PHY_PAD_DATA_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[926],
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0x7 << 6, mode_sel << 6);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x7 << 6,
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mode_sel << 6);
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/*PHY_927 PHY_PAD_DQS_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[926],
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0x7 << 6, mode_sel << 6);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x7 << 6,
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mode_sel << 6);
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/*PHY_928 PHY_PAD_ADDR_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[928],
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0x7 << 14, mode_sel << 14);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[928], 0x7 << 14,
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mode_sel << 14);
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/*PHY_929 PHY_PAD_CLK_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[929],
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0x7 << 14, mode_sel << 14);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[929], 0x7 << 14,
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mode_sel << 14);
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/*PHY_935 PHY_PAD_CKE_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[935],
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0x7 << 14, mode_sel << 14);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[935], 0x7 << 14,
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mode_sel << 14);
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/*PHY_937 PHY_PAD_RST_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[937],
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0x7 << 14, mode_sel << 14);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[937], 0x7 << 14,
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mode_sel << 14);
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/*PHY_939 PHY_PAD_CS_DRIVE*/
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clrsetbits_le32(&ddr_publ_regs->denali_phy[939],
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0x7 << 14, mode_sel << 14);
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clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0x7 << 14,
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mode_sel << 14);
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/*SPEED*/
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if (sdram_params->ddr_freq < 400*MHz)
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@ -470,29 +410,29 @@ static void phy_io_config(u32 channel,
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speed = 0x2;
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|
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/*PHY_924 PHY_PAD_FDBK_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[924],
|
||||
0x3 << 21, speed << 21);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[924], 0x3 << 21,
|
||||
speed << 21);
|
||||
/*PHY_926 PHY_PAD_DATA_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[926],
|
||||
0x3 << 9, speed << 9);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x3 << 9,
|
||||
speed << 9);
|
||||
/*PHY_927 PHY_PAD_DQS_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[926],
|
||||
0x3 << 9, speed << 9);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[926], 0x3 << 9,
|
||||
speed << 9);
|
||||
/*PHY_928 PHY_PAD_ADDR_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[928],
|
||||
0x3 << 17, speed << 17);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[928], 0x3 << 17,
|
||||
speed << 17);
|
||||
/*PHY_929 PHY_PAD_CLK_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[929],
|
||||
0x3 << 17, speed << 17);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[929], 0x3 << 17,
|
||||
speed << 17);
|
||||
/*PHY_935 PHY_PAD_CKE_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[935],
|
||||
0x3 << 17, speed << 17);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[935], 0x3 << 17,
|
||||
speed << 17);
|
||||
/*PHY_937 PHY_PAD_RST_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[937],
|
||||
0x3 << 17, speed << 17);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[937], 0x3 << 17,
|
||||
speed << 17);
|
||||
/*PHY_939 PHY_PAD_CS_DRIVE*/
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[939],
|
||||
0x3 << 17, speed << 17);
|
||||
clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0x3 << 17,
|
||||
speed << 17);
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue