mb/aopen/dxplplusu: Remove board
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
parent
6baee3d287
commit
eb76a455cd
63 changed files with 3 additions and 5323 deletions
|
|
@ -1,15 +0,0 @@
|
|||
if VENDOR_AOPEN
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
source "src/mainboard/aopen/*/Kconfig.name"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/aopen/*/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
default "AOpen"
|
||||
|
||||
endif # VENDOR_AOPEN
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config VENDOR_AOPEN
|
||||
bool "AOpen"
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
if BOARD_AOPEN_DXPLPLUSU
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select CPU_INTEL_SOCKET_MPGA604
|
||||
select NORTHBRIDGE_INTEL_E7505
|
||||
select SOUTHBRIDGE_INTEL_I82870
|
||||
select SOUTHBRIDGE_INTEL_I82801DX
|
||||
select SUPERIO_SMSC_LPC47M10X
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_2048
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "aopen/dxplplusu"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "DXPL Plus-U"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 12
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
endif # BOARD_AOPEN_DXPLPLUSU
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config BOARD_AOPEN_DXPLPLUSU
|
||||
bool "DXPL Plus-U"
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
bootblock-y += bootblock.c
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Device (MBRS)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C01"))
|
||||
Name (_UID, 0x01)
|
||||
Name (MSBF, ResourceTemplate ()
|
||||
{
|
||||
/* System memory */
|
||||
QWordMemory (ResourceProducer, PosDecode, MinFixed,
|
||||
MaxNotFixed, Prefetchable, ReadWrite,
|
||||
0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C,
|
||||
AddressRangeMemory, TypeStatic)
|
||||
|
||||
/* Top Of Low Memory */
|
||||
Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D)
|
||||
|
||||
/* 640kB who wants more? */
|
||||
Memory32Fixed (ReadWrite, 0x0, 0xA0000, )
|
||||
|
||||
/* 64k BIOS bootblock */
|
||||
Memory32Fixed (ReadOnly, 0xF0000, 0x10000,)
|
||||
|
||||
/* ISA memory hole 15-16 MB ? */
|
||||
/* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */
|
||||
/* ISA memory hole 14-15 MB ? */
|
||||
/* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */
|
||||
|
||||
/* Local APIC */
|
||||
Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,)
|
||||
})
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML)
|
||||
CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM)
|
||||
CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM)
|
||||
|
||||
And (\_SB.PCI0.RLAR, 0x03FF, Local1)
|
||||
Local1++
|
||||
If (Local1 > 0x40)
|
||||
{
|
||||
ShiftLeft (Local1, 0x1A, LELM)
|
||||
}
|
||||
|
||||
|
||||
CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00)
|
||||
CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01)
|
||||
CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2)
|
||||
And (\_SB.PCI0.TOLM, 0xF800, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
Local1--
|
||||
If (Local1 > 0x10)
|
||||
{
|
||||
Local1 -= 0x0F
|
||||
Store (ShiftLeft (Local1, 0x14), MEM2)
|
||||
Store (0x01000000, MS00)
|
||||
Store (MS00, MS01)
|
||||
}
|
||||
|
||||
Return (MSBF)
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
Name (PBRS, ResourceTemplate ()
|
||||
{
|
||||
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
|
||||
0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, )
|
||||
|
||||
/* System IO */
|
||||
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic)
|
||||
IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, )
|
||||
|
||||
/* Video RAM */
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, 0x000A0000, 0x000BFFFF,
|
||||
0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic)
|
||||
|
||||
/* Video ROM */
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, 0x000C0000, 0x000C7FFF,
|
||||
0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic)
|
||||
|
||||
/* Option ROMs ? */
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, 0x000C8000, 0x000DFFFF,
|
||||
0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic)
|
||||
|
||||
/* Top Of Lowmemory to IOAPIC */
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, 0x00000000, 0xFEBFFFFF,
|
||||
0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic)
|
||||
})
|
||||
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
|
||||
/* Top Of Lowmemory to IOAPIC */
|
||||
CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)
|
||||
CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH)
|
||||
CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)
|
||||
And (\_SB.PCI0.TOLM, 0xF800, Local1)
|
||||
ShiftRight (Local1, 0x04, Local1)
|
||||
ShiftLeft (Local1, 0x14, MEML)
|
||||
MEMH = IO_APIC_ADDR - 1
|
||||
LENM = IO_APIC_ADDR - MEML
|
||||
|
||||
Return (PBRS)
|
||||
}
|
||||
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
Device (USB0)
|
||||
{
|
||||
Name (_ADR, 0x001D0000)
|
||||
Name (_PRW, Package () { 0x03, 0x05 })
|
||||
|
||||
OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
|
||||
Field (USBS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xC4), URES, 8
|
||||
}
|
||||
}
|
||||
|
||||
Device (USB1)
|
||||
{
|
||||
Name (_ADR, 0x001D0001)
|
||||
Name (_PRW, Package () { 0x04, 0x05 })
|
||||
OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
|
||||
Field (USBS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xC4), URES, 8
|
||||
}
|
||||
}
|
||||
|
||||
Device (USB2)
|
||||
{
|
||||
Name (_ADR, 0x001D0002)
|
||||
Name (_PRW, Package () { 0x0C, 0x05 })
|
||||
OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
|
||||
Field (USBS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xC4), URES, 8
|
||||
}
|
||||
}
|
||||
|
||||
Device (USB3)
|
||||
{
|
||||
Name (_ADR, 0x001D0007)
|
||||
Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */
|
||||
OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
|
||||
Field (USBS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xC4), URES, 8
|
||||
}
|
||||
}
|
||||
|
||||
Device(PCI5)
|
||||
{
|
||||
Name (_ADR, 0x001E0000)
|
||||
Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x0003ffff, 0, 0, 20 },
|
||||
Package() { 0x0003ffff, 1, 0, 21 },
|
||||
Package() { 0x0003ffff, 2, 0, 22 },
|
||||
Package() { 0x0003ffff, 3, 0, 23 },
|
||||
})
|
||||
}
|
||||
|
||||
Device (ICH0)
|
||||
{
|
||||
Name (_ADR, 0x001F0000)
|
||||
OperationRegion (D310, PCI_Config, 0x00, 0xFF)
|
||||
Field (D310, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x40), PBAR, 16,
|
||||
Offset (0x58), GBAR, 16,
|
||||
}
|
||||
|
||||
OperationRegion (ACPI, SystemIO, 0x0400, 0xC0)
|
||||
Field (ACPI, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
PS1L, 8,
|
||||
PS1H, 8,
|
||||
PE1L, 8,
|
||||
PE1H, 8,
|
||||
|
||||
Offset (0x28),
|
||||
GS0L, 8,
|
||||
GS0H, 8,
|
||||
GSPL, 8,
|
||||
GSPH, 8,
|
||||
GE0L, 8,
|
||||
GE0H, 8,
|
||||
GEPL, 8,
|
||||
GEPH, 8,
|
||||
|
||||
Offset (0xB8),
|
||||
GPLV, 8
|
||||
}
|
||||
|
||||
Name (MSBF, ResourceTemplate ()
|
||||
{
|
||||
/* IOAPIC 0 */
|
||||
Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,)
|
||||
|
||||
IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO)
|
||||
IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO)
|
||||
|
||||
/* 8254 legacy irq */
|
||||
IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,)
|
||||
|
||||
/* reset generator */
|
||||
IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, )
|
||||
})
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1)
|
||||
CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2)
|
||||
CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL)
|
||||
|
||||
Store (PBAR, Local0)
|
||||
If (Local0 && 1)
|
||||
{
|
||||
And (Local0, 0xFFFE, Local0)
|
||||
Store (Local0, IOA1)
|
||||
Store (Local0, IOA2)
|
||||
Store (0x80, IOAL)
|
||||
} Else {
|
||||
Store (0x00, IOAL)
|
||||
}
|
||||
|
||||
CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1)
|
||||
CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2)
|
||||
CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL)
|
||||
|
||||
Store (GBAR, Local0)
|
||||
If (Local0 && 1) {
|
||||
And (Local0, 0xFFFE, Local0)
|
||||
Store (Local0, IOS1)
|
||||
Store (Local0, IOS2)
|
||||
Store (0x40, IOSL)
|
||||
} Else {
|
||||
Store (0x00, IOSL)
|
||||
}
|
||||
Return (MSBF)
|
||||
}
|
||||
|
||||
Device (FWH)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x01)
|
||||
|
||||
|
||||
Name (MSBG, ResourceTemplate () {
|
||||
Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,)
|
||||
Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,)
|
||||
})
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Return (MSBG)
|
||||
}
|
||||
}
|
||||
|
||||
Device (SMSC)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (_UID, 0x02)
|
||||
#include "acpi/superio.asl"
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Interrupt routing for PCI 03:xx.x */
|
||||
|
||||
/* I/O APIC id 0x3 */
|
||||
Device(PBIO)
|
||||
{
|
||||
Name (_ADR, 0x001c0000)
|
||||
}
|
||||
|
||||
/* PCI-X bridge */
|
||||
Device(P64B)
|
||||
{
|
||||
Name (_ADR, 0x001d0000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */
|
||||
Package() { 0x0002ffff, 1, 0, 25 },
|
||||
Package() { 0x0002ffff, 2, 0, 26 },
|
||||
Package() { 0x0002ffff, 3, 0, 27 },
|
||||
Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */
|
||||
Package() { 0x0003ffff, 1, 0, 29 },
|
||||
Package() { 0x0003ffff, 2, 0, 30 },
|
||||
Package() { 0x0003ffff, 3, 0, 31 },
|
||||
Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */
|
||||
})
|
||||
|
||||
Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
|
||||
OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
|
||||
Field (PBPC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x3E), BCRL, 8, BCRH, 8
|
||||
}
|
||||
|
||||
|
||||
Device (ETH0)
|
||||
{
|
||||
Name (_ADR, 0x00040000)
|
||||
Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Interrupt routing for PCI 04:xx.x */
|
||||
|
||||
/* I/O APIC id 0x4 */
|
||||
Device(PAIO)
|
||||
{
|
||||
Name (_ADR, 0x001e0000)
|
||||
}
|
||||
|
||||
/* PCI-X bridge */
|
||||
Device(P64A)
|
||||
{
|
||||
Name (_ADR, 0x001f0000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */
|
||||
Package() { 0x0002ffff, 1, 0, 49 },
|
||||
Package() { 0x0002ffff, 2, 0, 50 },
|
||||
Package() { 0x0002ffff, 3, 0, 51 },
|
||||
Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */
|
||||
Package() { 0x0003ffff, 1, 0, 53 },
|
||||
Package() { 0x0003ffff, 2, 0, 54 },
|
||||
Package() { 0x0003ffff, 3, 0, 55 },
|
||||
Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */
|
||||
Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */
|
||||
})
|
||||
|
||||
Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
|
||||
OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
|
||||
Field (PBPC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x3E), BCRL, 8, BCRH, 8
|
||||
}
|
||||
|
||||
#include "acpi/scsi.asl"
|
||||
}
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
/* Board powers on with button or PME# from on-board GbE wake-on-lan.
|
||||
* Board shuts down to S5/G2. Any other power management is untested.
|
||||
*/
|
||||
|
||||
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 })
|
||||
Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 })
|
||||
Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 })
|
||||
Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 })
|
||||
|
||||
Scope (\_GPE)
|
||||
{
|
||||
Method (_L03, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB0, 0x02)
|
||||
}
|
||||
Method (_L04, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB1, 0x02)
|
||||
}
|
||||
|
||||
/* WOL header */
|
||||
Method (_L08, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.PCI5, 0x02)
|
||||
Notify (\_SB.SLBT, 0x02)
|
||||
}
|
||||
|
||||
/* PME# */
|
||||
Method (_L0B, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.LID0, 0x02)
|
||||
}
|
||||
|
||||
Method (_L0C, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB2, 0x02)
|
||||
}
|
||||
|
||||
/* PME_B0_STS# */
|
||||
Method (_L0D, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.USB3, 0x02)
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear power buttons */
|
||||
Method (\_INI, 0, NotSerialized)
|
||||
{
|
||||
Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H)
|
||||
Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H)
|
||||
}
|
||||
|
||||
/* Prepare To Sleep */
|
||||
Method (\_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
|
||||
Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
|
||||
}
|
||||
|
||||
/* System Wake */
|
||||
Method (\_WAK, 1, NotSerialized)
|
||||
{
|
||||
Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
|
||||
Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
|
||||
|
||||
Return ( Package() { 0x0, 0x0 } )
|
||||
}
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W
|
||||
* U320 SCSI dual-channel controller
|
||||
*/
|
||||
|
||||
Device (SCS0)
|
||||
{
|
||||
Name (_ADR, 0x00040000)
|
||||
OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
|
||||
Field (SCSC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x2C), SID, 32,
|
||||
Offset (0xE0), PMC, 8,
|
||||
Offset (0xFF), IDW, 8
|
||||
}
|
||||
}
|
||||
|
||||
Device (SCS1)
|
||||
{
|
||||
Name (_ADR, 0x00040001)
|
||||
OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
|
||||
Field (SCSC, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x2C), SID, 32,
|
||||
Offset (0xE0), PMC, 8,
|
||||
Offset (0xFF), IDW, 8
|
||||
}
|
||||
}
|
||||
|
|
@ -1,161 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
/* SuperIO GPIO configuration via logical device 0x0A */
|
||||
|
||||
Name (MSBF, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B)
|
||||
})
|
||||
|
||||
OperationRegion (LPC0, SystemIO, 0x0E00, 0x60)
|
||||
Field (LPC0, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
PME0, 8,
|
||||
Offset (0x02), PME2,8,
|
||||
Offset (0x04), PME4,8,
|
||||
Offset (0x0A), PMEA,8,
|
||||
Offset (0x23),
|
||||
GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8,
|
||||
GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8,
|
||||
GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8,
|
||||
GC40,8, GC41,8, GC42,8, GC43,8,
|
||||
|
||||
Offset (0x3F),
|
||||
GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8,
|
||||
GC60,8, GC61,8,
|
||||
|
||||
Offset (0x4B),
|
||||
GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8,
|
||||
Offset (0x56), FAN1,8,
|
||||
Offset (0x5D), LED1,8, LED2,8,
|
||||
}
|
||||
|
||||
OperationRegion (SMC1, SystemIO, 0x2E, 0x02)
|
||||
Field (SMC1, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
INDX, 8, DATA, 8
|
||||
}
|
||||
|
||||
IndexField (INDX, DATA, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0x07), LDN, 8,
|
||||
Offset (0x22), PWRC, 8,
|
||||
Offset (0x30), ACTR, 8,
|
||||
Offset (0x60),
|
||||
IOAH, 8, IOAL, 8,
|
||||
IOBH, 8, IOBL, 8,
|
||||
|
||||
Offset (0x70), INTR, 8,
|
||||
Offset (0x72), INT1, 8,
|
||||
Offset (0x74), DMCH, 8,
|
||||
Offset (0xB2), SPS1, 8, SPS2, 8,
|
||||
Offset (0xB8), D2TS, 8,
|
||||
Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8,
|
||||
Offset (0xF4), WDTC, 8,
|
||||
Offset (0xF6), GP01, 8, GP02, 8, GP04, 8
|
||||
}
|
||||
|
||||
Method (ECFG, 0, NotSerialized)
|
||||
{
|
||||
Store (0x55, INDX)
|
||||
}
|
||||
Method (XCFG, 0, NotSerialized)
|
||||
{
|
||||
Store (0xAA, INDX)
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1)
|
||||
CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2)
|
||||
CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML)
|
||||
|
||||
ECFG ()
|
||||
Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN)
|
||||
Store (0x00, IOM1)
|
||||
Store (0x00, IOM2)
|
||||
Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1)
|
||||
ShiftLeft (IOM1, 0x08, IOM1)
|
||||
Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1)
|
||||
Store (IOM1, IOM2)
|
||||
If (IOM1 != 0)
|
||||
{
|
||||
Store (0x80, IOML)
|
||||
}
|
||||
XCFG ()
|
||||
|
||||
Return (MSBF)
|
||||
}
|
||||
|
||||
|
||||
Method (_INI, 0, NotSerialized)
|
||||
{
|
||||
/* GPIO configuration */
|
||||
Store (0x00, GC10)
|
||||
Store (0x81, GC11)
|
||||
Store (0x00, GC17)
|
||||
Store (0x0c, GC21)
|
||||
Store (0x00, GC22)
|
||||
Store (0x04, GC27)
|
||||
Store (0x04, GC30)
|
||||
Store (0x01, GC31)
|
||||
Store (0x01, GC32)
|
||||
Store (0x01, GC33)
|
||||
Store (0x01, GC34) /* GPI password jumper */
|
||||
Store (0x01, GC35) /* GPI scsi enable jumper */
|
||||
Store (0x01, GC42) /* GPI */
|
||||
Store (0x86, GC60) /* led 1 */
|
||||
Store (0x81, GC61) /* led 2 ?? */
|
||||
|
||||
/* GPIO initial output levels */
|
||||
Store (GP_1, Local0)
|
||||
And( Local0, 0x7C, Local0)
|
||||
Or ( Local0, 0x81, Local0)
|
||||
Store (Local0, GP_1)
|
||||
|
||||
Store (GP_2, Local0)
|
||||
And( Local0, 0xFE, Local0)
|
||||
Or ( Local0, 0x00, Local0)
|
||||
Store (Local0, GP_2)
|
||||
|
||||
Store (GP_3, Local0)
|
||||
And( Local0, 0x7F, Local0)
|
||||
Or ( Local0, 0x80, Local0)
|
||||
Store (Local0, GP_3)
|
||||
|
||||
Store (GP_4, Local0)
|
||||
And( Local0, 0x7F, Local0)
|
||||
Or ( Local0, 0x00, Local0)
|
||||
Store (Local0, GP_4)
|
||||
|
||||
/* Power Led */
|
||||
Store (LED1, Local0)
|
||||
And( Local0, 0xfc, Local0)
|
||||
Or ( Local0, 0x01, Local0)
|
||||
Store (Local0, LED1)
|
||||
|
||||
}
|
||||
|
||||
Method (MLED, 1, NotSerialized)
|
||||
{
|
||||
If (LEqual (Arg0, 0x00))
|
||||
{
|
||||
Store (0x00, LED1)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, 0x01) || LEqual (Arg0, 0x02))
|
||||
{
|
||||
Store (0x01, LED1)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, 0x03))
|
||||
{
|
||||
Store (0x02, LED1)
|
||||
}
|
||||
|
||||
If (LEqual (Arg0, 0x04) || LEqual (Arg0, 0x05))
|
||||
{
|
||||
Store (0x03, LED1)
|
||||
}
|
||||
}
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/*
|
||||
* Ported to Intel XE7501DEVKIT by Agami Aruma
|
||||
* Ported to AOpen DXPL Plus-U by Kyösti Mälkki
|
||||
*/
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <device/pci_def.h>
|
||||
|
||||
#define IOAPIC_ICH4 2
|
||||
#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 */
|
||||
#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 */
|
||||
|
||||
#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
unsigned int irq_start = 0;
|
||||
struct device *bdev, *dev = NULL;
|
||||
struct resource* res = NULL;
|
||||
|
||||
/* SJM: Hard-code CPU LAPIC entries for now */
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
|
||||
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
|
||||
|
||||
/* Southbridge IOAPIC */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4,
|
||||
0xfec00000, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
|
||||
bdev = pcidev_on_root(2, 0);
|
||||
/* P64H2 Bus B IOAPIC */
|
||||
if (bdev)
|
||||
dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(28, 0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
|
||||
IOAPIC_P64H2_BUS_B, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
}
|
||||
|
||||
/* P64H2 Bus A IOAPIC */
|
||||
if (bdev)
|
||||
dev = pcidev_path_behind(bdev->link_list, PCI_DEVFN(30, 0));
|
||||
if (dev) {
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
|
||||
IOAPIC_P64H2_BUS_A, res->base, irq_start);
|
||||
irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
|
||||
}
|
||||
|
||||
/* Map ISA IRQ 0 to IRQ 2 */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
|
||||
|
||||
/* IRQ9 differs from ISA standard - ours is active high, level-triggered */
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
Category: server
|
||||
Board URL: ftp://ftp.aopen.com/pub/server/motherboard/dxplpu/manual/dxplpu-ol-e.pdf
|
||||
ROM package: PLCC
|
||||
ROM protocol: FWH
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <superio/smsc/lpc47m10x/lpc47m10x.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
/* Get the serial port configured. */
|
||||
lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/intel/e7505
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604
|
||||
device lapic 0 on end
|
||||
device lapic 6 on end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 0.0 on end # Chipset host controller
|
||||
device pci 0.1 on end # Host RASUM controller
|
||||
device pci 2.0 on # Hub interface B
|
||||
chip southbridge/intel/i82870 # P64H2
|
||||
device pci 1c.0 on end # IOAPIC - bus B
|
||||
device pci 1d.0 on end # Hub to PCI-B bridge
|
||||
device pci 1e.0 on end # IOAPIC - bus A
|
||||
device pci 1f.0 on end # Hub to PCI-A bridge
|
||||
end
|
||||
end
|
||||
device pci 4.0 off end # (undocumented)
|
||||
device pci 6.0 off end # (undocumented)
|
||||
chip southbridge/intel/i82801dx
|
||||
device pci 1d.0 on end # USB UHCI
|
||||
device pci 1d.1 on end # USB UHCI
|
||||
device pci 1d.2 on end # USB UHCI
|
||||
device pci 1d.7 on end # USB EHCI
|
||||
device pci 1e.0 on # Hub to PCI bridge
|
||||
device pci 2.0 off end
|
||||
end
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/smsc/lpc47m10x
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 off # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # Keyboard interrupt
|
||||
irq 0x72 = 12 # Mouse interrupt
|
||||
end
|
||||
device pnp 2e.a on # ACPI
|
||||
io 0x60 = 0x0e00
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # IDE
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 on end # AC97 Audio
|
||||
device pci 1f.6 off end # AC97 Modem
|
||||
end # SB
|
||||
end # PCI domain
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20111103 // OEM revision
|
||||
) {
|
||||
#include <acpi/dsdt_top.asl>
|
||||
|
||||
Scope(\_SB)
|
||||
{
|
||||
Device(PCI0) {
|
||||
Name (_HID, EISAID("PNP0A03"))
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x001dffff, 0, 0, 16 },
|
||||
Package() { 0x001dffff, 1, 0, 19 },
|
||||
Package() { 0x001dffff, 2, 0, 18 },
|
||||
Package() { 0x001dffff, 3, 0, 23 },
|
||||
Package() { 0x001fffff, 0, 0, 18 },
|
||||
Package() { 0x001fffff, 1, 0, 17 },
|
||||
})
|
||||
|
||||
#include "acpi/e7505_sec.asl"
|
||||
|
||||
OperationRegion (I750, PCI_Config, 0x00, 0x0100)
|
||||
Field (I750, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Offset (0xC4),
|
||||
TOLM, 16, /* Top of Low Memory */
|
||||
RBAR, 16, /* REMAP_BASE */
|
||||
RLAR, 16 /* REMAP_LIMIT */
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/e7505_pri.asl"
|
||||
|
||||
|
||||
Device (PWBT)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0C"))
|
||||
Name (_PRW, Package () { 0x08, 0x05 })
|
||||
}
|
||||
|
||||
Device (SLBT)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0E"))
|
||||
Name (_PRW, Package () { 0x0B, 0x05 })
|
||||
}
|
||||
|
||||
Device (LID0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C0D"))
|
||||
Name (_PRW, Package () { 0x0B, 0x05 })
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
Scope(\_SB.PCI0)
|
||||
{
|
||||
|
||||
Device(PCI1)
|
||||
{
|
||||
Name (_ADR, 0x00010000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x0000ffff, 0, 0, 16 },
|
||||
Package() { 0x0000ffff, 1, 0, 17 },
|
||||
})
|
||||
}
|
||||
|
||||
Device(HLIB)
|
||||
{
|
||||
Name (_ADR, 0x00020000)
|
||||
Name (_PRT, Package() {
|
||||
Package() { 0x001dffff, 0, 0, 18 },
|
||||
Package() { 0x001dffff, 1, 0, 18 },
|
||||
Package() { 0x001dffff, 2, 0, 18 },
|
||||
Package() { 0x001dffff, 3, 0, 18 },
|
||||
Package() { 0x001fffff, 0, 0, 18 },
|
||||
Package() { 0x001fffff, 1, 0, 18 },
|
||||
Package() { 0x001fffff, 2, 0, 18 },
|
||||
Package() { 0x001fffff, 3, 0, 18 },
|
||||
})
|
||||
|
||||
#include "acpi/p64h2.asl"
|
||||
}
|
||||
|
||||
#include "acpi/i82801db.asl"
|
||||
}
|
||||
|
||||
#include "acpi/power.asl"
|
||||
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue