From eb528621321c38337ed214c0cb487530b36d8ee9 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Fri, 28 Nov 2025 15:56:58 +0800 Subject: [PATCH] mb/google/brox/var/caboc: Update SSD port and FPMCU setting Start from next stage, Caboc route SSD to PEG60 and change SSD CLK_SRC CLK_OUT, SSD_CLKREQ(GPP_D8-SRCCLKREQ3#) to port 3. This CL updates PEG60 CLK_SRC, CLK_OUT to port 3, sets NF1 to GPP_D8- SRCCLKREQ3. Update fingerprint PCH_FP_BOOT0 to GPP_D5. Remove PEG62 settings include vGPIO, set NC GPP_H23 (SRCCLKREQ5#), set NC GPP_F20 (EN_PP3300_SSD) follow schematic 1128A. BUG=b:464243569, b:45604227, b:441591974 TEST=emerge-brox coreboot Change-Id: I4376b6532b412215e39be499806e7ebd2eac9841 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/90259 Tested-by: build bot (Jenkins) Reviewed-by: Wisley Chen --- .../google/brox/variants/caboc/fw_config.c | 12 ++---- .../google/brox/variants/caboc/gpio.c | 42 +++++-------------- .../brox/variants/caboc/overridetree.cb | 23 ++-------- 3 files changed, 17 insertions(+), 60 deletions(-) diff --git a/src/mainboard/google/brox/variants/caboc/fw_config.c b/src/mainboard/google/brox/variants/caboc/fw_config.c index 092c45ba69..6f5d09d2e0 100644 --- a/src/mainboard/google/brox/variants/caboc/fw_config.c +++ b/src/mainboard/google/brox/variants/caboc/fw_config.c @@ -7,8 +7,8 @@ #include static const struct pad_config fp_disable_pads[] = { - /* GPP_D8 : PCH_FP_BOOT0 */ - PAD_NC(GPP_D8, NONE), + /* GPP_D5 : PCH_FP_BOOT0 */ + PAD_NC(GPP_D5, NONE), /* GPP_D9 : FP_RST_ODL */ PAD_NC(GPP_D9, NONE), /* GPP_D11 : [] ==> EN_FP_PWR */ @@ -49,12 +49,8 @@ static const struct pad_config lte_disable_pads[] = { static const struct pad_config nvme_disable_pads[] = { /* GPP_F9 : SSD_PERST_L */ PAD_NC(GPP_F9, NONE), - /* GPP_F20 : EN_PP3300_SSD */ - PAD_NC(GPP_F20, NONE), - /* GPP_D5 : SSD_CLKREQ_ODL */ - PAD_NC(GPP_D5, NONE), - /* GPP_H23 : SSD_CLKREQ5_ODL */ - PAD_NC(GPP_H23, NONE), + /* GPP_D8 : SSD_CLKREQ_ODL */ + PAD_NC(GPP_D8, NONE), }; static void fw_config_handle(void *unused) diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c index 7a683eacc4..db88777526 100644 --- a/src/mainboard/google/brox/variants/caboc/gpio.c +++ b/src/mainboard/google/brox/variants/caboc/gpio.c @@ -21,12 +21,12 @@ static const struct pad_config override_gpio_table[] = { /* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> WWAN_GPS_XMIT_OFF */ PAD_CFG_GPO(GPP_D4, 0, DEEP), - /* GPP_D5 : SRCCLKREQ0_L ==> SSD_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D5 : SRCCLKREQ0_L ==> PCH_FP_BOOT0 */ + PAD_CFG_GPO_LOCK(GPP_D5, 0, LOCK_CONFIG), /* GPP_D7 : SRCCLKREQ2_L ==> PCIE_CLKREQ_LAN */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - /* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> PCH_FP_BOOT0 */ - PAD_CFG_GPO_LOCK(GPP_D8, 0, LOCK_CONFIG), + /* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */ PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG), /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP(NC) */ @@ -65,13 +65,13 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ_WWAN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_F20, 1, DEEP), + /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> NC */ + PAD_NC(GPP_F20, NONE), /* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/ PAD_CFG_GPO(GPP_F21, 1, DEEP), - /* GPP_H23 : SRCCLKREQ5_L ==> */ - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + /* GPP_H23 : SRCCLKREQ5_L ==> NC */ + PAD_NC(GPP_H23, NONE), }; /* Early pad configuration in bootblock */ @@ -102,8 +102,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_F9, 0, DEEP), - /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_F20, 1, DEEP), + /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> NC */ + PAD_NC(GPP_F20, NONE), /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ @@ -115,28 +115,6 @@ static const struct pad_config early_gpio_table[] = { /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_S0, NONE, DEEP), - /* CPU PCIe vGPIO for RP2 */ - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1), - PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1), - /* CPU PCIe vGPIO for PEG60 */ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb index 6cf5defcdc..9816c123c1 100644 --- a/src/mainboard/google/brox/variants/caboc/overridetree.cb +++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb @@ -273,30 +273,13 @@ chip soc/intel/alderlake end end device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 5 + # Enable CPU PCIE RP 1 using CLK 3 register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .clk_req = 5, - .clk_src = 5, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - probe STORAGE STORAGE_NVME - probe unprovisioned - end - device ref pcie4_1 on - # Enable CPU PCIE RP 3 using CLK 0 - register "cpu_pcie_rp[CPU_RP(3)]" = "{ - .clk_req = 0, - .clk_src = 0, + .clk_req = 3, + .clk_src = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L1, }" - chip soc/intel/common/block/pcie/rtd3 - register "is_storage" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F9)" - register "srcclk_pin" = "0" - device generic 0 on end - end probe STORAGE STORAGE_NVME probe unprovisioned end