From eb005f5f5c7ab1c59720475a24903f6d5c94dee1 Mon Sep 17 00:00:00 2001 From: Curtis Chen Date: Fri, 18 Jul 2025 16:12:27 +0800 Subject: [PATCH] mb/google/brya/var: Clarify comment for 'tcss_aux_ori' For the latest trulo projects: kaladin,pujjolo,pujjocent, the original comment was too brief and led to some misunderstanding. In the past years, only retimer has the SBU muxing function. Or said, only retimer has Aux Orientation feature. So, 'no retimer' implies Aux Orientation feature inside the processor is needed. And now, the modern future PDC also has the Aux Orientation feature. Not all "no retimer" cases require setting the override bit anymore. The even numbered bits should be set only when there is no retimer and the processor's Aux Orientation is still required. (If set, the SoC inverts the orientation value coming from EC/PDC when operating in flipped orientation.) In the referenced issue tracker, the system has 'no retimer' and uses a 'future PDC'. (The PDC has the Aux Orientation feature.) Test results (DP + TCSS): - 'tcss_aux_ori' = 0 + PDC sends orientation detected value -> PASS - 'tcss_aux_ori' = 5 + PDC sends 'original' value -> PASS - 'tcss_aux_ori' = 5 + PDC sends orientation detected value -> FAIL (Fail means only display one side.) This patch updates the comment to more accurately describe the expected usage and avoid future confusion. Refer doc#: 646929 TWL PDG 734752 TCSS Cookbook (MTL Backward/MTL/PTL/WCL) 627270 TWL Bios Spec 758766 MTL Bios Spec 766031 MTL PDG BUG=b:4292672 BRANCH=none TEST=Update coreboot device tree with different tcss_aux_ori value and test the DP connection via TCSS on 2 orientations. Change-Id: I3281110e522c53a35abf30fd1c372bb5ca18c10d Signed-off-by: Curtis Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/88482 Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/kaladin/overridetree.cb | 5 ++++- .../google/brya/variants/pujjocento/overridetree.cb | 5 ++++- src/mainboard/google/brya/variants/pujjolo/overridetree.cb | 5 ++++- 3 files changed, 12 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb index c58dc8659d..b46584a491 100644 --- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb +++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb @@ -52,7 +52,10 @@ chip soc/intel/alderlake # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. # TcssAuxOri = 0101b - # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor. + # This only should be set when no retimer is present and processor-level Aux Orientation + # is still needed. (E.g. The PDC does not have Aux Orientation feature.) + # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1". # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the # motherboard to USBC connector register "tcss_aux_ori" = "0" diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb index d84f1000ea..cdf996e53a 100644 --- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -60,7 +60,10 @@ chip soc/intel/alderlake # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. # TcssAuxOri = 0101b - # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor. + # This only should be set when no retimer is present and processor-level Aux Orientation + # is still needed. (E.g. The PDC does not have Aux Orientation feature.) + # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1". # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the # motherboard to USBC connector register "tcss_aux_ori" = "0" diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb index a68adf5425..e79d5988e7 100644 --- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb @@ -52,7 +52,10 @@ chip soc/intel/alderlake # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. # TcssAuxOri = 0101b - # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor. + # This only should be set when no retimer is present and processor-level Aux Orientation + # is still needed. (E.g. The PDC does not have Aux Orientation feature.) + # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1". # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the # motherboard to USBC connector register "tcss_aux_ori" = "0"