diff --git a/src/mainboard/google/brya/variants/kaladin/overridetree.cb b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
index c58dc8659d..b46584a491 100644
--- a/src/mainboard/google/brya/variants/kaladin/overridetree.cb
+++ b/src/mainboard/google/brya/variants/kaladin/overridetree.cb
@@ -52,7 +52,10 @@ chip soc/intel/alderlake
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
 	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
 	# TcssAuxOri = 0101b
-	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor.
+        # This only should be set when no retimer is present and processor-level Aux Orientation
+        # is still needed. (E.g. The PDC does not have Aux Orientation feature.)
+        # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1".
 	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "0"
diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
index d84f1000ea..cdf996e53a 100644
--- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb
@@ -60,7 +60,10 @@ chip soc/intel/alderlake
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
 	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
 	# TcssAuxOri = 0101b
-	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor.
+        # This only should be set when no retimer is present and processor-level Aux Orientation
+        # is still needed. (E.g. The PDC does not have Aux Orientation feature.)
+        # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1".
 	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "0"
diff --git a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
index a68adf5425..e79d5988e7 100644
--- a/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/pujjolo/overridetree.cb
@@ -52,7 +52,10 @@ chip soc/intel/alderlake
 	# This is a bitfield that corresponds to up to 4 TCSS ports.
 	# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
 	# TcssAuxOri = 0101b
-	# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
+	# Set Bit0 and Bit2 to "1" to enable the Aux Orientation feature inside the processor.
+        # This only should be set when no retimer is present and processor-level Aux Orientation
+        # is still needed. (E.g. The PDC does not have Aux Orientation feature.)
+        # Bits 0 and 2 must be enabled first before configuring Bits 1 and 3 to be "1".
 	# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
 	# motherboard to USBC connector
 	register "tcss_aux_ori" = "0"