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Coding style fixes and cosmetic changes (trivial).

Browse source 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@249 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-03-12 02:50:03 +00:00
commit eaf86e6a50
4 changed files with 75 additions and 68 deletions
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1
northbridge/intel/i440bxemulation/config.h
View file

@ -20,6 +20,7 @@
extern struct device_operations i440bxemulation_pcidomainops;
extern struct constructor i440bx_constructors[];
struct northbridge_intel_i440bx_config {
/* The various emulators don't always get 440BX right. So we are
* going to allow users to set the RAM size via Kconfig.

101
northbridge/intel/i440bxemulation/i440bx.c
View file

@ -28,46 +28,50 @@
#include "i440bx.h"
/* Here are the ops for 440BX as a PCI domain. */
/* a PCI domain contains the I/O and memory resource address space below it. */
/* A PCI domain contains the I/O and memory resource address space below it. */
static void pci_domain_read_resources(struct device * dev)
static void pci_domain_read_resources(struct device *dev)
{
struct resource *resource;
struct resource *resource;
/* Initialize the system wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags =
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags =
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(struct device * dev, unsigned long index,
unsigned long basek, unsigned long sizek)
static void ram_resource(struct device *dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
struct resource *resource;
if (!sizek) {
return;
}
resource = new_resource(dev, index);
resource->base = ((resource_t)basek) << 10;
resource->size = ((resource_t)sizek) << 10;
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
printk(BIOS_INFO, "%s: add ram resoource %d bytes\n", __func__, resource->size);
if (!sizek) {
return;
}
resource = new_resource(dev, index);
resource->base = ((resource_t) basek) << 10;
resource->size = ((resource_t) sizek) << 10;
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
printk(BIOS_INFO, "%s: add ram resoource %d bytes\n", __func__,
resource->size);
}
static void pci_domain_set_resources(struct device * dev)
static void pci_domain_set_resources(struct device *dev)
{
struct device * mc_dev;
u32 tolmk; /* Top of low mem, Kbytes. */
struct device *mc_dev;
u32 tolmk; /* Top of low mem, Kbytes. */
int idx;
struct northbridge_intel_i440bx_config *device_configuration = dev->device_configuration;
tolmk = device_configuration->ramsize * 1024;
struct northbridge_intel_i440bx_config *device_configuration =
dev->device_configuration;
tolmk = device_configuration->ramsize * 1024;
mc_dev = dev->link[0].children;
if (mc_dev) {
idx = 10;
@ -76,33 +80,34 @@ static void pci_domain_set_resources(struct device * dev)
phase4_assign_resources(&dev->link[0]);
}
static unsigned int pci_domain_scan_bus(struct device * dev, unsigned int max)
static unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max)
{
/* there is only one link on this device, and it is always link 0 */
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
/* There is only one link on this device, and it is always link 0. */
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
/* here are the operations for when the northbridge is running a pci domain. */
/* see emulation/qemu-x86 for an example of how these are used. */
/* Here are the operations for when the northbridge is running a PCI domain. */
/* See mainboard/emulation/qemu-x86 for an example of how these are used. */
struct device_operations i440bxemulation_pcidomainops = {
.constructor = default_device_constructor,
.phase3_scan = pci_domain_scan_bus,
.phase4_read_resources = pci_domain_read_resources,
.phase4_set_resources = pci_domain_set_resources,
.phase5_enable_resources = enable_childrens_resources,
.phase6_init = 0,
.ops_pci_bus = &pci_cf8_conf1,
.constructor = default_device_constructor,
.phase3_scan = pci_domain_scan_bus,
.phase4_read_resources = pci_domain_read_resources,
.phase4_set_resources = pci_domain_set_resources,
.phase5_enable_resources = enable_childrens_resources,
.phase6_init = 0,
.ops_pci_bus = &pci_cf8_conf1,
};
/* the constructor for the device. */
/* the plain PCI device uses the standard PCI operations. */
/* The constructor for the device. */
/* The plain PCI device uses the standard PCI operations. */
struct constructor i440bx_constructors[] = {
{.id={.type=DEVICE_ID_PCI_DOMAIN, .u={.pci={.vendor=0x8086, .device=0x7190}}},
&i440bxemulation_pcidomainops},
{.id={.type=DEVICE_ID_PCI, .u={.pci={.vendor=0x8086, .device=0x7190}}},
&default_pci_ops_bus},
{.id = {.type = DEVICE_ID_PCI_DOMAIN,
.u = {.pci = {.vendor = 0x8086,.device = 0x7190}}},
&i440bxemulation_pcidomainops},
{.id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7190}}},
&default_pci_ops_bus},
{.ops = 0},
};

5
southbridge/intel/i82371eb/config.h
View file

@ -19,8 +19,7 @@
*/
extern struct constructor i82371eb_constructors[];
struct southbridge_intel_i82371eb_config
{
struct southbridge_intel_i82371eb_config {
int ide;
};

36
southbridge/intel/i82371eb/i82371eb.c
View file

@ -27,34 +27,36 @@
#include "config.h"
// #include "i82371eb.h"
/* The plain PCI device uses the standard PCI operations. */
/* Note that this structure is not necessary (yet),
* but is here as an example of how you can set up your own ops
/* Note that this structure is not necessary (yet),
* but is here as an example of how you can set up your own ops.
*/
/* You can override or extend each of these operations as needed for the device. */
/* You can override or extend each operation as needed for the device. */
static struct device_operations i82371eb_pci_ops_dev = {
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_enable_disable = 0,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pci_dev_init,
.ops_pci = &pci_dev_ops_pci,
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase4_enable_disable = 0,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pci_dev_init,
.ops_pci = &pci_dev_ops_pci,
};
struct constructor i82371eb_constructors[] = {
{.id={.type=DEVICE_ID_PCI, .u={.pci={.vendor=0x8086, .device=0x7110}}},
{.id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7110}}},
&i82371eb_pci_ops_dev},
{.id={.type=DEVICE_ID_PCI, .u={.pci={.vendor=0x8086, .device=0x7111}}},
{.id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7111}}},
&i82371eb_pci_ops_dev},
{.id={.type=DEVICE_ID_PCI, .u={.pci={.vendor=0x8086, .device=0x7112}}},
{.id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7112}}},
&i82371eb_pci_ops_dev},
{.id={.type=DEVICE_ID_PCI, .u={.pci={.vendor=0x8086, .device=0x7113}}},
{.id = {.type = DEVICE_ID_PCI,
.u = {.pci = {.vendor = 0x8086,.device = 0x7113}}},
&i82371eb_pci_ops_dev},
{.ops = 0},
};