diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h index 54c7c64a5f..ab4bfca85c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.
+Copyright (c) 2025, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h index a85327d3c6..a4184fc592 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.
+Copyright (c) 2025, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -308,9 +308,9 @@ typedef struct { **/ UINT8 TrainTrace; -/** Offset 0x0177 - Reserved +/** Offset 0x0177 **/ - UINT8 Reserved0; + UINT8 UnusedUpdSpace0; /** Offset 0x0178 - Tseg Size Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build @@ -407,9 +407,11 @@ typedef struct { **/ UINT8 PchHdaAudioLinkDmicClockSelect[2]; -/** Offset 0x019A - Reserved +/** Offset 0x019A - PchPreMemRsvd + Reserved for PCH Pre-Mem Reserved + $EN_DIS **/ - UINT8 Reserved1[5]; + UINT8 PchPreMemRsvd[5]; /** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set @@ -423,9 +425,9 @@ typedef struct { **/ UINT8 DmaControlGuarantee; -/** Offset 0x01A1 - Reserved +/** Offset 0x01A1 **/ - UINT8 Reserved2[3]; + UINT8 UnusedUpdSpace1[3]; /** Offset 0x01A4 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -493,9 +495,14 @@ typedef struct { **/ UINT8 UserBd; -/** Offset 0x01D1 - Reserved +/** Offset 0x01D1 - MRC Retraining on RTC Power Loss + Specifies whether MRC memory training will occur when RTC power loss is detected. + Options are 0=Memory will be re-trained if RTC power loss is detected. 1=Memory + will not be re-trained when RTC power loss is detected. (Typically used on board + designs without a dedicated RTC battery) + 0:Disabled, 1:Enabled **/ - UINT8 Reserved3; + UINT8 DisableMrcRetrainingOnRtcPowerLoss; /** Offset 0x01D2 - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, @@ -598,9 +605,9 @@ typedef struct { **/ UINT8 RefClk; -/** Offset 0x01E3 - Reserved +/** Offset 0x01E3 **/ - UINT8 Reserved4; + UINT8 UnusedUpdSpace2; /** Offset 0x01E4 - Memory Voltage DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM @@ -627,9 +634,9 @@ typedef struct { **/ UINT8 tCWL; -/** Offset 0x01E9 - Reserved +/** Offset 0x01E9 **/ - UINT8 Reserved5; + UINT8 UnusedUpdSpace3; /** Offset 0x01EA - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected @@ -649,9 +656,9 @@ typedef struct { **/ UINT8 tRCDtRP; -/** Offset 0x01EF - Reserved +/** Offset 0x01EF **/ - UINT8 Reserved6; + UINT8 UnusedUpdSpace4; /** Offset 0x01F0 - tREFI Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected @@ -804,9 +811,9 @@ typedef struct { **/ UINT8 PsmiRegionSize; -/** Offset 0x0221 - Reserved +/** Offset 0x0221 **/ - UINT8 Reserved7[3]; + UINT8 UnusedUpdSpace5[3]; /** Offset 0x0224 - Temporary MMIO address for GMADR Obsolete field now and it has been extended to 64 bit address, used GmAdr64 @@ -1046,9 +1053,9 @@ typedef struct { **/ UINT8 DdiPort4Ddc; -/** Offset 0x0289 - Reserved +/** Offset 0x0289 **/ - UINT8 Reserved8[7]; + UINT8 UnusedUpdSpace6[7]; /** Offset 0x0290 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR @@ -1072,9 +1079,9 @@ typedef struct { **/ UINT8 SaVoltageMode; -/** Offset 0x029B - Reserved +/** Offset 0x029B **/ - UINT8 Reserved9; + UINT8 UnusedUpdSpace7; /** Offset 0x029C - SA/Uncore Voltage Override The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override @@ -1103,9 +1110,73 @@ typedef struct { **/ UINT8 TvbVoltageOptimization; -/** Offset 0x02A2 - Reserved +/** Offset 0x02A2 - Enable/Disable Display Audio Link in Pre-OS + 0(Default)= Disable, 1 = Enable + 0: Disabled, 1: Enabled **/ - UINT8 Reserved10[111]; + UINT8 DisplayAudioLink; + +/** Offset 0x02A3 +**/ + UINT8 UnusedUpdSpace8; + +/** Offset 0x02A4 - Memory VDDQ Voltage + DRAM voltage (Vddq) (supply voltage for DQ/DQS of the DRAM chips) in millivolts + from 0 - default to 1435mv. +**/ + UINT16 VddqVoltage; + +/** Offset 0x02A6 - Memory VPP Voltage + DRAM voltage (Vpp) (supply voltage for VPP of the DRAM chips) in millivolts from + 0 - default to 2135mv. +**/ + UINT16 VppVoltage; + +/** Offset 0x02A8 - CPU PCIe New FOM + Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 CpuPcieNewFom[4]; + +/** Offset 0x02AC - DMI DEKEL New FOM + Enable/Disable NewFom for DEKEL Programming. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 DmiNewFom; + +/** Offset 0x02AD - Dynamic Memory Boost + 0(Default): Disable, 1: Enable. When enabled, MRC will train the Default SPD Profile, + and also the profile selected by SpdProfileSelected, to allow automatic switching + during runtime. Only valid if SpdProfileSelected is an XMP Profile, otherwise ignored. + $EN_DIS +**/ + UINT8 DynamicMemoryBoost; + +/** Offset 0x02AE - Hybrid Graphics Support + 0(Default): PEG10, 1: PEG60, 2:PEG62. Help to select Hybrid Graphics Support on Peg Port +**/ + UINT8 HgSupport; + +/** Offset 0x02AF - Realtime Memory Frequency + 0(Default): Disabled, 1: Enabled. Ignored unless SpdProfileSelected is an XMP Profile. + If enabled, MRC will train the Default SPD Profile, and also the selected XMP Profile, + to allow manually triggered switching between frequencies at runtime. + $EN_DIS +**/ + UINT8 RealtimeMemoryFrequency; + +/** Offset 0x02B0 - OC Safe Mode + 0: Disabled, 1(Default): Enabled. Ignored unless SpdProfileSelected is an XMP Profile. + If enabled, MRC will use less aggressive controls when training memory. + $EN_DIS +**/ + UINT8 OCSafeMode; + +/** Offset 0x02B1 - SaPreMemProductionRsvd + Reserved for SA Pre-Mem Production + $EN_DIS +**/ + UINT8 SaPreMemProductionRsvd[96]; /** Offset 0x0311 - Enable Gt CLOS 0(Default)=Disable, 1=Enable @@ -1273,9 +1344,83 @@ typedef struct { **/ UINT8 DmiGen3UsPortTxPreset[8]; -/** Offset 0x037B - Reserved +/** Offset 0x037B - DMI Hw Eq Gen4 CoeffList Cm + CPU_PCIE_EQ_PARAM. Coefficient C-1. **/ - UINT8 Reserved11[54]; + UINT8 CpuDmiHwEqGen4CoeffListCm[8]; + +/** Offset 0x0383 - DMI Hw Eq Gen4 CoeffList Cp + CPU_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 CpuDmiHwEqGen4CoeffListCp[8]; + +/** Offset 0x038B - Enable/Disable CPU DMI GEN4 Phase 23 Bypass + CPU DMI GEN4 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): + Enable Phase 23 Bypass + $EN_DIS +**/ + UINT8 Gen4EqPhase23Bypass; + +/** Offset 0x038C - Enable/Disable CPU DMI GEN4 Phase 3 Bypass + CPU DMI GEN3 Phase 4 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): + Enable Phase 3 Bypass + $EN_DIS +**/ + UINT8 Gen4EqPhase3Bypass; + +/** Offset 0x038D - Enable/Disable DMI GEN4 DmiGen4DsPresetEnable + Enable/Disable DMI GEN4 DmiGen4DsPreset. Auto(0x0)(Default): DmiGen4DsPresetEnable, + Manual(0x1): Enable DmiGen4DsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen4DsPresetEnable; + +/** Offset 0x038E - DMI Gen4 Root port preset Tx values per lane + Used for programming DMI Gen4 preset values per lane. Range: 0-10, 7 is default + for each lane +**/ + UINT8 DmiGen4DsPortTxPreset[8]; + +/** Offset 0x0396 - Enable/Disable CPU DMI Gen4 EQ Remote Transmitter Coefficient/Preset Override Enable + Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): + Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote + Transmitter Coefficient/Preset Override + $EN_DIS +**/ + UINT8 Gen4RtcoRtpoEnable; + +/** Offset 0x0397 - Enable/Disable CPU DMI Gen4 EQ Local Transmitter Coefficient Override Enable + Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): + Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter + Coefficient Override + $EN_DIS +**/ + UINT8 Gen4LtcoEnable; + +/** Offset 0x0398 - DMI Gen4 Transmitter Pre-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Pre-Cursor Coefficient . Range: 0-10, + 7 is default for each lane +**/ + UINT8 DmiGen4Ltcpre[8]; + +/** Offset 0x03A0 - DMI Gen4 Transmitter Post-Cursor Coefficient + Used for programming DMI Gen4 Transmitter Post-Cursor Coefficient. Range: 0-9, 7 + is default for each lane +**/ + UINT8 DmiGen4Ltcpo[8]; + +/** Offset 0x03A8 - Enable/Disable DMI GEN4 DmiGen4UsPresetEnable + Enable/Disable DMI GEN4 DmiGen4UsPreset. Auto(0x0)(Default): DmiGen4UsPresetEnable, + Manual(0x1): Enable DmiGen4UsPresetEnable + $EN_DIS +**/ + UINT8 DmiGen4UsPresetEnable; + +/** Offset 0x03A9 - DMI Gen4 Root port preset Tx values per lane + Used for programming DMI Gen4 preset values per lane. Range: 0-10, 1 is default + for each lane +**/ + UINT8 DmiGen4UsPortTxPreset[8]; /** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo Set ASPM Control configuration @@ -1430,9 +1575,10 @@ typedef struct { **/ UINT8 CorePllVoltageOffset; -/** Offset 0x03CD - Reserved +/** Offset 0x03CD - Atom Core PLL voltage offset + Atom Core PLL voltage offset. 0: No offset. Range 0-15 **/ - UINT8 Reserved12; + UINT8 AtomPllVoltageOffset; /** Offset 0x03CE - Ring Downbin Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always @@ -1453,9 +1599,9 @@ typedef struct { **/ UINT8 TjMaxOffset; -/** Offset 0x03D1 - Reserved +/** Offset 0x03D1 **/ - UINT8 Reserved13; + UINT8 UnusedUpdSpace9; /** Offset 0x03D2 - Ring voltage override The ring voltage override which is applied to the entire range of cpu ring frequencies. @@ -1499,9 +1645,72 @@ typedef struct { **/ UINT8 DebugInterfaceLockEnable; -/** Offset 0x03DC - Reserved +/** Offset 0x03DC - Atom L2 voltage mode + Atom L2 voltage mode; 0: Adaptive; 1: Override. + $EN_DIS **/ - UINT8 Reserved14[24]; + UINT8 AtomL2VoltageMode; + +/** Offset 0x03DD +**/ + UINT8 UnusedUpdSpace10; + +/** Offset 0x03DE - Atom L2 Voltage Override + The atom L2 voltage override which is applied to the entire range of atom L2 frequencies. + Valid Range 0 to 2000 +**/ + UINT16 AtomL2VoltageOverride; + +/** Offset 0x03E0 - Atom L2 Turbo voltage Adaptive + Extra Turbo voltage applied to the atom L2 when the atom L2 is operating in turbo + mode. Valid Range 0 to 2000 +**/ + UINT16 AtomL2VoltageAdaptive; + +/** Offset 0x03E2 - Atom L2 Turbo voltage Offset + The voltage offset applied to the atom while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 AtomL2VoltageOffset; + +/** Offset 0x03E4 - Per-Atom-Cluster VF Offset + Array used to specifies the selected Atom Core Cluster Offset Voltage. This voltage + is specified in millivolts. +**/ + UINT16 PerAtomClusterVoltageOffset[4]; + +/** Offset 0x03EC - Per-Atom-Cluster VF Offset Prefix + Sets the PerAtomClusterVoltageOffset value as positive or negative for the selected + Core; 0: Positive ; 1: Negative. +**/ + UINT8 PerAtomClusterVoltageOffsetPrefix[4]; + +/** Offset 0x03F0 - Enable IA CEP + Control for enabling/disabling IA CEP (Current Excursion Protection)). 1: Enable; + 0: Disable + $EN_DIS +**/ + UINT8 IaCepEnable; + +/** Offset 0x03F1 - Enable GT CEP + Control for enabling/disabling GT CEP (Current Excursion Protection)). 1: Enable; + 0: Disable + $EN_DIS +**/ + UINT8 GtCepEnable; + +/** Offset 0x03F2 - Enable CPU DLVR bypass mode support + DEPRECATED + $EN_DIS +**/ + UINT8 DlvrBypassModeEnable; + +/** Offset 0x03F3 - Number of active small cores + Number of active small cores(Depends on Number of small cores). Default 0xFF means + to active all system supported small cores. 0xFF: Active all small cores; + 0: Disable all small cores; 1: 1; 2: 2; 3: 3; + 0:Disable all small cores, 1:1, 2:2, 3:3, 0xFF:Active all small cores +**/ + UINT8 ActiveSmallCoreCount; /** Offset 0x03F4 - Core VF Point Offset Mode Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. @@ -1511,9 +1720,9 @@ typedef struct { **/ UINT8 CoreVfPointOffsetMode; -/** Offset 0x03F5 - Reserved +/** Offset 0x03F5 **/ - UINT8 Reserved15; + UINT8 UnusedUpdSpace11[1]; /** Offset 0x03F6 - Core VF Point Offset Array used to specifies the Core Voltage Offset applied to the each selected VF @@ -1538,9 +1747,24 @@ typedef struct { **/ UINT8 CoreVfPointCount; -/** Offset 0x0433 - Reserved +/** Offset 0x0433 - Core VF Configuration Scope + Alows both all-core VF curve or per-core VF curve configuration; 0: All-core; + 1: Per-core. + 0:All-core, 1:Per-core **/ - UINT8 Reserved16[25]; + UINT8 CoreVfConfigScope; + +/** Offset 0x0434 - Per-core VF Offset + Array used to specifies the selected Core Offset Voltage. This voltage is specified + in millivolts. +**/ + UINT16 PerCoreVoltageOffset[8]; + +/** Offset 0x0444 - Per-core VF Offset Prefix + Sets the PerCoreVoltageOffset value as positive or negative for the selected Core; + 0: Positive ; 1: Negative. +**/ + UINT8 PerCoreVoltageOffsetPrefix[8]; /** Offset 0x044C - Per Core Max Ratio override Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new @@ -1554,9 +1778,18 @@ typedef struct { **/ UINT8 PerCoreRatio[8]; -/** Offset 0x0455 - Reserved +/** Offset 0x0455 - Atom Cluster Max Ratio + Array for Atom Cluster Max Ratio, 4 ATOM cores are in the same Cluster and their + max core ratio will be aligned. **/ - UINT8 Reserved17[5]; + UINT8 AtomClusterRatio[4]; + +/** Offset 0x0459 - Core Ratio Extension Mode + Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to + enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable + $EN_DIS +**/ + UINT8 CoreRatioExtensionMode; /** Offset 0x045A - Pvd Ratio Threshold Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default. @@ -1576,9 +1809,35 @@ typedef struct { **/ UINT8 CrashLogGprs; -/** Offset 0x045D - Reserved +/** Offset 0x045D - Ring VF Point Offset Mode + Selects Ring Voltage & Frequency Offset mode between Legacy and Selection modes. + In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, + setting a selected VF point; 0: Legacy; 1: Selection. + 0:Legacy, 1:Selection **/ - UINT8 Reserved18[62]; + UINT8 RingVfPointOffsetMode; + +/** Offset 0x045E - Ring VF Point Offset + Array used to specifies the Ring Voltage Offset applied to the each selected VF + Point. This voltage is specified in millivolts. +**/ + UINT16 RingVfPointOffset[15]; + +/** Offset 0x047C - Ring VF Point Offset Prefix + Sets the RingVfPointOffset value as positive or negative for corresponding core + VF Point; 0: Positive ; 1: Negative. +**/ + UINT8 RingVfPointOffsetPrefix[15]; + +/** Offset 0x048B - Ring VF Point Ratio + Array for the each selected Ring VF Point to display the ration. +**/ + UINT8 RingVfPointRatio[15]; + +/** Offset 0x049A - Ring VF Point Count + Number of supported Ring Voltage & Frequency Point Offset +**/ + UINT8 RingVfPointCount; /** Offset 0x049B - BCLK Frequency Source Clock source of BCLK OC frequency, 1:CPU BCLK, 2:PCH BCLK, 3:External CLK @@ -1593,9 +1852,9 @@ typedef struct { **/ UINT8 GpioOverride; -/** Offset 0x049D - Reserved +/** Offset 0x049D **/ - UINT8 Reserved19[3]; + UINT8 UnusedUpdSpace12[3]; /** Offset 0x04A0 - CPU BCLK OC Frequency CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 @@ -1603,9 +1862,144 @@ typedef struct { **/ UINT32 CpuBclkOcFrequency; -/** Offset 0x04A4 - Reserved +/** Offset 0x04A4 - Bitmask of disable cores + Core mask is a bitwise indication of which core should be disabled. 0x00=Default; + Bit 0 - core 0, bit 7 - core 7. **/ - UINT8 Reserved20[40]; + UINT32 DisablePerCoreMask; + +/** Offset 0x04A8 - Bitmask of disable atoms + DEPRECATED +**/ + UINT32 DisablePerAtomMask; + +/** Offset 0x04AC - Sa PLL Frequency + Configure Sa PLL Frequency. 0: 3200MHz , 1: 1600MHz + 0: 3200MHz, 1: 1600MHz +**/ + UINT8 SaPllFreqOverride; + +/** Offset 0x04AD - Skip override boot mode When Fw Update. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to + BOOT_WITH_FULL_CONFIGURATION in PEI memory init. + $EN_DIS +**/ + UINT8 SiSkipOverrideBootModeWhenFwUpdate; + +/** Offset 0x04AE - TSC HW Fixup disable + TSC HW Fixup disable during TSC copy from PMA to APIC. 0: Enable; 1: Disable + 0:Enable, 1:Disable +**/ + UINT8 TscDisableHwFixup; + +/** Offset 0x04AF - Support IA Unlimited ICCMAX + Support IA Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 IaIccUnlimitedMode; + +/** Offset 0x04B0 - IA ICCMAX + IA ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 4 + . Range is 4-2047. +**/ + UINT16 IaIccMax; + +/** Offset 0x04B2 - Support GT Unlimited ICCMAX + Support GT Unlimited ICCMAX up to maximum value 512A; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 GtIccUnlimitedMode; + +/** Offset 0x04B3 +**/ + UINT8 UnusedUpdSpace13; + +/** Offset 0x04B4 - GT ICCMAX + GT ICCMAX value is represented in 1/4 A increments. A value of 400 = 100A. 4 + . Range is 4-2047. +**/ + UINT16 GtIccMax; + +/** Offset 0x04B6 - TVB Down Bins for Temp Threshold 0 + Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold + 0, the ratio will be clipped by MAX_RATIO[n]-This value, when TVB ratio clipping + is enabled. Default is 1. +**/ + UINT8 TvbDownBinsTempThreshold0; + +/** Offset 0x04B7 - TVB Temperature Threshold 0 + TVB Temp (degrees C) - Temperature Threshold 0. Running ABOVE this temperature will + clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when TVB ratio + clipping is enabled. Default is 70. +**/ + UINT8 TvbTempThreshold0; + +/** Offset 0x04B8 - TVB Temperature Threshold 1 + TVB Temp (degrees C) - Temperature Threshold 1. Running ABOVE this temperature will + clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when TVB ratio + clipping is enabled. Default is 100. +**/ + UINT8 TvbTempThreshold1; + +/** Offset 0x04B9 - TVB Down Bins for Temp Threshold 1 + Down Bins (delta) for Temperature Threshold 1. When running above Temperature Threshold + 1, the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 1-This value, when + TVB ratio clipping is enabled. Default is 2. +**/ + UINT8 TvbDownBinsTempThreshold1; + +/** Offset 0x04BA - FLL Overclock Mode Enable + Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking + with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated + (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated + (3-5x) reference clock frequency and ratio limited to 63. + $EN_DIS +**/ + UINT8 FllOcModeEn; + +/** Offset 0x04BB - FLL Overclock Mode + Select FLL Mode Value from 0 to 3. 0x0 = no overclocking, 0x1 = ratio overclocking + with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated + (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated + (3-5x) reference clock frequency and ratio limited to 63. +**/ + UINT8 FllOverclockMode; + +/** Offset 0x04BC - Configuration for boot TDP selection + Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP + Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x04BD +**/ + UINT8 UnusedUpdSpace14[3]; + +/** Offset 0x04C0 - Short term Power Limit value for custom cTDP level 1 + Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 CustomPowerLimit1; + +/** Offset 0x04C4 - Enhanced Thermal Turbo Mode + When eTVB mode is enabled user will be clipped when temperatures reach 70C 0: + Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 Etvb; + +/** Offset 0x04C5 - UnderVolt Protection + When UnderVolt Protection is enabled, user will be not be able to program under + voltage in OS runtime. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 UnderVoltProtection; + +/** Offset 0x04C6 - ReservedCpuPreMem + Reserved for Cpu Pre-Mem + $EN_DIS +**/ + UINT8 ReservedCpuPreMem[6]; /** Offset 0x04CC - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1623,9 +2017,9 @@ typedef struct { **/ UINT8 Txt; -/** Offset 0x04CF - Reserved +/** Offset 0x04CF **/ - UINT8 Reserved21; + UINT8 UnusedUpdSpace15; /** Offset 0x04D0 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1687,9 +2081,11 @@ typedef struct { **/ UINT8 IsTPMPresence; -/** Offset 0x0509 - Reserved +/** Offset 0x0509 - ReservedSecurityPreMem + Reserved for Security Pre-Mem + $EN_DIS **/ - UINT8 Reserved22[32]; + UINT8 ReservedSecurityPreMem[32]; /** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1874,9 +2270,9 @@ typedef struct { **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0745 - Reserved +/** Offset 0x0745 **/ - UINT8 Reserved23; + UINT8 UnusedUpdSpace16; /** Offset 0x0746 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1895,18 +2291,32 @@ typedef struct { **/ UINT8 PcieClkSrcUsage[18]; -/** Offset 0x075B - Reserved +/** Offset 0x075B **/ - UINT8 Reserved24[14]; + UINT8 PcieClkSrcUsageRsvd[14]; /** Offset 0x0769 - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[18]; -/** Offset 0x077B - Reserved +/** Offset 0x077B **/ - UINT8 Reserved25[93]; + UINT8 PcieClkSrcClkReqRsvd[14]; + +/** Offset 0x0789 +**/ + UINT8 UnusedUpdSpace17[3]; + +/** Offset 0x078C - Clk Req GPIO Pin + Select Clk Req Pin. Refer to GPIO_*_MUXING_SRC_CLKREQ_x* for possible values. +**/ + UINT32 PcieClkReqGpioMux[18]; + +/** Offset 0x07D4 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT32 RsvdSmbusAddressTablePtr; /** Offset 0x07D8 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -1966,9 +2376,9 @@ typedef struct { **/ UINT8 PchHdaDspEnable; -/** Offset 0x07F5 - Reserved +/** Offset 0x07F5 **/ - UINT8 Reserved26[3]; + UINT8 UnusedUpdSpace18[3]; /** Offset 0x07F8 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* @@ -2028,9 +2438,9 @@ typedef struct { **/ UINT8 SerialIoUartDebugAutoFlow; -/** Offset 0x0811 - Reserved +/** Offset 0x0811 **/ - UINT8 Reserved27[3]; + UINT8 UnusedUpdSpace19[3]; /** Offset 0x0814 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -2056,9 +2466,9 @@ typedef struct { **/ UINT8 SerialIoUartDebugDataBits; -/** Offset 0x081B - Reserved +/** Offset 0x081B **/ - UINT8 Reserved28; + UINT8 UnusedUpdSpace20; /** Offset 0x081C - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2376,9 +2786,11 @@ typedef struct { **/ UINT8 ChHashEnable; -/** Offset 0x0854 - Reserved +/** Offset 0x0854 - Ch Hash Settings Override + Channel Hash Settings Override + $EN_DIS **/ - UINT8 Reserved29; + UINT8 ChHashOverride; /** Offset 0x0855 - Extern Therm Status Enables/Disable Extern Therm Status @@ -2416,9 +2828,11 @@ typedef struct { **/ UINT8 ThrtCkeMinDefeat; -/** Offset 0x085B - Reserved +/** Offset 0x085B - Row Hammer Select + Row Hammer Select + 0:Disable, 1:RFM, 2:pTRR **/ - UINT8 Reserved30; + UINT8 RhSelect; /** Offset 0x085C - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2522,9 +2936,17 @@ typedef struct { **/ UINT8 RMTBIT; -/** Offset 0x086D - Reserved +/** Offset 0x086D - ECC DFT feature + Enables/Disable ECC DFT feature + $EN_DIS **/ - UINT8 Reserved31[2]; + UINT8 EccDftEn; + +/** Offset 0x086E - Write0 feature + Enables/Disable Write0 feature + $EN_DIS +**/ + UINT8 Write0; /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -2581,9 +3003,11 @@ typedef struct { **/ UINT8 EWRDSEQ; -/** Offset 0x087E - Reserved +/** Offset 0x087E - MC_REFRESH_2X_MODE + DEPRECATED + $EN_DIS **/ - UINT8 Reserved32; + UINT8 McRefresh2X; /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) @@ -2791,9 +3215,16 @@ typedef struct { **/ UINT8 ThrtCkeMinTmr; -/** Offset 0x08A8 - Reserved +/** Offset 0x08A8 - Allow Opp Ref Below Write Threhold + Allow opportunistic refreshes while we don't exit power down. + $EN_DIS **/ - UINT8 Reserved33[2]; + UINT8 AllowOppRefBelowWriteThrehold; + +/** Offset 0x08A9 - Write Threshold + Number of writes that can be accumulated while CKE is low before CKE is asserted. +**/ + UINT8 WriteThreshold; /** Offset 0x08AA - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2823,9 +3254,10 @@ typedef struct { **/ UINT8 EpgEnable; -/** Offset 0x08AF - Reserved +/** Offset 0x08AF - RH pTRR LFSR0 Mask + Row Hammer pTRR LFSR0 Mask, 1/2^(value) **/ - UINT8 Reserved34; + UINT8 Lfsr0Mask; /** Offset 0x08B0 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2897,9 +3329,9 @@ typedef struct { **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x08BB - Reserved +/** Offset 0x08BB **/ - UINT8 Reserved35; + UINT8 UnusedUpdSpace21; /** Offset 0x08BC - Post Code Output Port This option configures Post Code Output Port @@ -2924,9 +3356,9 @@ typedef struct { **/ UINT8 WrcFeatureEnable; -/** Offset 0x08C1 - Reserved +/** Offset 0x08C1 **/ - UINT8 Reserved36[3]; + UINT8 UnusedUpdSpace22[3]; /** Offset 0x08C4 - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2974,9 +3406,20 @@ typedef struct { **/ UINT8 Ddr4OneDpc; -/** Offset 0x08DB - Reserved +/** Offset 0x08DB - RH pTRR LFSR1 Mask + Row Hammer pTRR LFSR1 Mask, 1/2^(value) **/ - UINT8 Reserved37[3]; + UINT8 Lfsr1Mask; + +/** Offset 0x08DC - LPDDR ODT RttWr + Initial RttWr for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttWr; + +/** Offset 0x08DD - LPDDR ODT RttCa + Initial RttCa for LP4/5 in Ohms. 0x0 - Auto +**/ + UINT8 LpddrRttCa; /** Offset 0x08DE - REFRESH_PANIC_WM DEPRECATED @@ -3000,9 +3443,59 @@ typedef struct { **/ UINT8 CmdMirror; -/** Offset 0x08E2 - Reserved +/** Offset 0x08E2 - DIMM DFE Training + Enable/Disable DIMM DFE Training + $EN_DIS **/ - UINT8 Reserved38[9]; + UINT8 DIMMDFE; + +/** Offset 0x08E3 - Extended Bank Hashing + Enable/Disable Extended Bank Hashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x08E4 - Refresh Watermarks + Refresh Watermarks: 0-Low, 1-High (default) + 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default) +**/ + UINT8 RefreshWm; + +/** Offset 0x08E5 - MC_REFRESH_RATE + Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh + 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh +**/ + UINT8 McRefreshRate; + +/** Offset 0x08E6 - Periodic DCC + Enable/Disable Periodic DCC; default: Disabled + $EN_DIS +**/ + UINT8 PeriodicDcc; + +/** Offset 0x08E7 - LpMode + LpMode feature + 0: Auto (default), 1: Enabled, 2: Disabled, 3: Reserved +**/ + UINT8 LpMode; + +/** Offset 0x08E8 - TX DQS DCC Training + Enable/Disable TX DQS DCC Training + $EN_DIS +**/ + UINT8 TXDQSDCC; + +/** Offset 0x08E9 - DRAM DCA Training + Enable/Disable DRAM DCA Training + $EN_DIS +**/ + UINT8 DRAMDCA; + +/** Offset 0x08EA - EARLY DIMM DFE Training + Enable/Disable EARLY DIMM DFE Training + $EN_DIS +**/ + UINT8 EARLYDIMMDFE; /** Offset 0x08EB - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -3023,9 +3516,13 @@ typedef struct { **/ UINT8 LockPTMregs; -/** Offset 0x08EE - Reserved +/** Offset 0x08EE - Rsvd + Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): + Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE + peak values unmodified + $EN_DIS **/ - UINT8 Reserved39; + UINT8 PegGen3Rsvd; /** Offset 0x08EF - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -3040,9 +3537,9 @@ typedef struct { **/ UINT8 BdatTestType; -/** Offset 0x08F1 - Reserved +/** Offset 0x08F1 **/ - UINT8 Reserved40[3]; + UINT8 UnusedUpdSpace23[3]; /** Offset 0x08F4 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3054,9 +3551,44 @@ typedef struct { **/ UINT8 PreBootDmaMask; -/** Offset 0x08F9 - Reserved +/** Offset 0x08F9 **/ - UINT8 Reserved41[95]; + UINT8 UnusedUpdSpace24; + +/** Offset 0x08FA - Delta T12 Power Cycle Delay required in ms + Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate + T12 Delay to max 500ms + 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay +**/ + UINT16 DeltaT12PowerCycleDelay; + +/** Offset 0x08FC - Reuse Adl DDR5 Board or not + Indicate whether adl ddr5 board is reused. + 0 : no, 1 : yes +**/ + UINT8 ReuseAdlSDdr5Board; + +/** Offset 0x08FD - Oem T12 Delay Override + Oem T12 Delay Override. 0(Default)=Disable 1=Enable + $EN_DIS +**/ + UINT8 OemT12DelayOverride; + +/** Offset 0x08FE - DQS Offset Adjust Training + Enable/Disable DQS Offset Adjust Training + $EN_DIS +**/ + UINT8 DQSOFFSETADJUST; + +/** Offset 0x08FF - SaPreMemTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS +**/ + UINT8 SaPreMemTestRsvd[88]; + +/** Offset 0x0957 +**/ + UINT8 UnusedUpdSpace25; /** Offset 0x0958 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -3070,9 +3602,11 @@ typedef struct { **/ UINT16 BiosSize; -/** Offset 0x095C - Reserved +/** Offset 0x095C - SecurityTestRsvd + Reserved for SA Pre-Mem Test + $EN_DIS **/ - UINT8 Reserved42[12]; + UINT8 SecurityTestRsvd[12]; /** Offset 0x0968 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -3136,9 +3670,9 @@ typedef struct { **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x0972 - Reserved +/** Offset 0x0972 **/ - UINT8 Reserved43[2]; + UINT8 UnusedUpdSpace26[2]; /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs @@ -3173,9 +3707,9 @@ typedef struct { **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x0A97 - Reserved +/** Offset 0x0A97 **/ - UINT8 Reserved44; + UINT8 UnusedUpdSpace27; /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -3199,9 +3733,257 @@ typedef struct { **/ UINT32 SerialIoUartDebugCtsPinMux; -/** Offset 0x0AA8 - Reserved +/** Offset 0x0AA8 - Ppr Enable Type + Enable Soft or Hard PPR 0:Disable, 2:Hard PPR + 0:Disable, 2:Hard PPR **/ - UINT8 Reserved45[130]; + UINT8 PprEnable; + +/** Offset 0x0AA9 - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x0AAA - Margin Limit L2 + % of L1 check for margin limit check +**/ + UINT16 MarginLimitL2; + +/** Offset 0x0AAC - DEKEL CDR Relock + Enable/Disable CDR Relock. 0: Disable(Default); 1: Enable +**/ + UINT8 CpuPcieRpCdrRelock[4]; + +/** Offset 0x0AB0 - DMI DEKEL CDR Relock + Enable/Disable CPU DMI CDR Relock. 0: Disable(Default); 1: Enable + $EN_DIS +**/ + UINT8 DmiCdrRelock; + +/** Offset 0x0AB1 - IbeccErrInjControl + IBECC Error Injection Control + 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable + Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject + Uncorrectable Error on insertion counter +**/ + UINT8 IbeccErrInjControl; + +/** Offset 0x0AB2 +**/ + UINT8 UnusedUpdSpace28[6]; + +/** Offset 0x0AB8 - IbeccErrInjAddress + Address to match against for ECC error injection +**/ + UINT64 IbeccErrInjAddress; + +/** Offset 0x0AC0 - IbeccErrInjMask + Mask to match against for ECC error injection +**/ + UINT64 IbeccErrInjMask; + +/** Offset 0x0AC8 - IbeccErrInjCount + Number of transactions between ECC error injection +**/ + UINT32 IbeccErrInjCount; + +/** Offset 0x0ACC - Pointer EnableDmaBuffer + Pointer of EnableDmaBuffer Callback Function. +**/ + UINT8 EnableDmaBuffer[8]; + +/** Offset 0x0AD4 - PLL Max Banding Ratio + DEPRECATED +**/ + UINT8 PllMaxBandingRatio; + +/** Offset 0x0AD5 +**/ + UINT8 UnusedUpdSpace29[3]; + +/** Offset 0x0AD8 - Debug Value + Debug Value +**/ + UINT32 DebugValue; + +/** Offset 0x0ADC - Pre-Mem GPIO table address + AlderLake S needs to assert PCIe SLOT RTD3 and PEG reset pins in early PreMem phase. + 0: Skip FSP PCIe pins programming. Refer to mAdlSPcieRstPinGpioTable[] in GpioSampleDef.h. +**/ + UINT32 BoardGpioTablePreMemAddress; + +/** Offset 0x0AE0 - tRFCpb + Min Internal per bank refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used + if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT16 tRFCpb; + +/** Offset 0x0AE2 - tRFC2 + Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC2; + +/** Offset 0x0AE4 - tRFC4 + Min Internal refresh recovery delay time, 0: AUTO, max: 0xFFFF. Only used if FspmUpd->FspmConfig.SpdProfileSelected + == 1 (Custom Profile). +**/ + UINT16 tRFC4; + +/** Offset 0x0AE6 - tRRD_L + Min Internal row active to row active delay time for same bank groups, 0: AUTO, + max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRRD_L; + +/** Offset 0x0AE7 - tRRD_S + Min Internal row active to row active delay time for different bank groups, 0: AUTO, + max: 80. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tRRD_S; + +/** Offset 0x0AE8 - tWTR_L + Min Internal write to read command delay time for same bank groups, 0: AUTO, max: + 127. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tWTR_L; + +/** Offset 0x0AE9 - tCCD_L + Min Internal CAS-to-CAS delay for same bank group, 0: AUTO, max: 80. Only used if + FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tCCD_L; + +/** Offset 0x0AEA - tWTR_S + Min Internal write to read command delay time for different bank groups, 0: AUTO, + max: 50. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). +**/ + UINT8 tWTR_S; + +/** Offset 0x0AEB +**/ + UINT8 UnusedUpdSpace30[5]; + +/** Offset 0x0AF0 - EccErrInjAddress + Address to match against for ECC error injection +**/ + UINT64 EccErrInjAddress; + +/** Offset 0x0AF8 - EccErrInjMask + Mask to match against for ECC error injection +**/ + UINT64 EccErrInjMask; + +/** Offset 0x0B00 - EccErrInjCount + Number of transactions between ECC error injection +**/ + UINT32 EccErrInjCount; + +/** Offset 0x0B04 - Frequency Limit for 2DPC Mixed or non-POR Config + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto (default), otherwise a + frequency in MT/s +**/ + UINT16 FreqLimitMixedConfig; + +/** Offset 0x0B06 - First Dimm BitMask + Defines which DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, Bit1: + MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM to be + populated should be set to '1' +**/ + UINT8 FirstDimmBitMask; + +/** Offset 0x0B07 - SAGV Switch Factor IA DDR BW + SAGV Switch Factor IA DDR BW: IA DDR load percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorIA; + +/** Offset 0x0B08 - SAGV Switch Factor GT DDR BW + SAGV Switch Factor GT DDR BW: GT DDR load percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorGT; + +/** Offset 0x0B09 - SAGV Switch Factor IO DDR BW + SAGV Switch Factor IO DDR BW: IO DDR load percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorIO; + +/** Offset 0x0B0A - SAGV Switch Factor IA and GT Stall + SAGV Switch Factor IA and GT Stall: IA and GT percentage when system switch to high + SAGV point from 1 to 50%. +**/ + UINT8 SagvSwitchFactorStall; + +/** Offset 0x0B0B - Threshold For Switch Down + SAGV heuristics down control: Duration in ms of low activity after which SAGV will + switch down, from 1 to 50ms. +**/ + UINT8 SagvHeuristicsDownControl; + +/** Offset 0x0B0C - Threshold For Switch Up + SAGV heuristics up control: Duration in ms of low activity after which SAGV will + switch up, from 1 to 50ms. +**/ + UINT8 SagvHeuristicsUpControl; + +/** Offset 0x0B0D +**/ + UINT8 UnusedUpdSpace31; + +/** Offset 0x0B0E - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 8GB + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_1R1R_8GB; + +/** Offset 0x0B10 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 16GB and 16GB + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_1R1R_16GB; + +/** Offset 0x0B12 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 16GB + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; + +/** Offset 0x0B14 - Frequency Limit for Mixed 2DPC DDR5 2 Rank + Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency + in MT/s, default is 2000 +**/ + UINT16 FreqLimitMixedConfig_2R2R; + +/** Offset 0x0B16 - DMI Hw Eq Gen3 CoeffList Cm + PCH_DMI_EQ_PARAM. Coefficient C-1. +**/ + UINT8 PchDmiHwEqGen3CoeffListCm[8]; + +/** Offset 0x0B1E - DMI Hw Eq Gen3 CoeffList Cp + PCH_DMI_EQ_PARAM. Coefficient C+1. +**/ + UINT8 PchDmiHwEqGen3CoeffListCp[8]; + +/** Offset 0x0B26 - LCT Command eyewidth + LCT Command eyewidth. 0: Auto, otherwise eyewidth , default is 96 +**/ + UINT16 LctCmdEyeWidth; + +/** Offset 0x0B28 - For LPDDR Only: Throttler CKEMin Timer + For LPDDR Only: Timer value for CKEMin, range[255;0]. Reqd min of SC_ROUND_T + BYTE_LENGTH + (4). Dfault is 0x00 +**/ + UINT8 ThrtCkeMinTmrLpddr; + +/** Offset 0x0B29 - First ECC Dimm BitMask + Defines which ECC DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, + Bit1: MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM + to be populated should be set to '1' +**/ + UINT8 FirstDimmBitMaskEcc; /** Offset 0x0B2A - LP5 Bank Mode LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0 @@ -3209,9 +3991,31 @@ typedef struct { **/ UINT8 Lp5BankMode; -/** Offset 0x0B2B - Reserved +/** Offset 0x0B2B - Write DS Training + Enable/Disable Write DS Training + $EN_DIS **/ - UINT8 Reserved46[13]; + UINT8 WRDS; + +/** Offset 0x0B2C - SAM Overlaoding + Enable: copy the sagv frequency point. Disable: not copy. + $EN_DIS +**/ + UINT8 OverloadSAM; + +/** Offset 0x0B2D - Time Measure + Time Measure: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 MrcTimeMeasure; + +/** Offset 0x0B2E +**/ + UINT8 UnusedUpdSpace32[5]; + +/** Offset 0x0B33 +**/ + UINT8 ReservedFspmUpd2[5]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h index b5e96c1846..96e4686009 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/twinlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2022 - 2024, Intel Corporation. All rights reserved.
+Copyright (c) 2025, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -123,9 +123,9 @@ typedef struct { **/ UINT8 ShowSpiController; -/** Offset 0x0056 - Reserved +/** Offset 0x0056 **/ - UINT8 Reserved0[2]; + UINT8 UnusedUpdSpace0[2]; /** Offset 0x0058 - MicrocodeRegionBase Memory Base of Microcode Updates @@ -161,9 +161,14 @@ typedef struct { **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x0072 - Reserved +/** Offset 0x0072 **/ - UINT8 Reserved1[34]; + UINT8 UnusedUpdSpace1[2]; + +/** Offset 0x0074 - SATA DEVSLP GPIO Pin + Select SATA DEVSLP Pin. Refer to GPIO_*_MUXING_SATA_DEVSLP_x* for possible values. +**/ + UINT32 SataPortDevSlpPinMux[8]; /** Offset 0x0094 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for @@ -183,9 +188,9 @@ typedef struct { **/ UINT8 XdciEnable; -/** Offset 0x00AF - Reserved +/** Offset 0x00AF **/ - UINT8 Reserved2; + UINT8 UnusedUpdSpace2; /** Offset 0x00B0 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. @@ -231,9 +236,9 @@ typedef struct { **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x00C2 - Reserved +/** Offset 0x00C2 **/ - UINT8 Reserved3[2]; + UINT8 UnusedUpdSpace3[2]; /** Offset 0x00C4 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. @@ -299,9 +304,9 @@ typedef struct { **/ UINT8 SerialIoUartMode[7]; -/** Offset 0x010A - Reserved +/** Offset 0x010A **/ - UINT8 Reserved4[2]; + UINT8 UnusedUpdSpace4[2]; /** Offset 0x010C - Default BaudRate for each Serial IO UART Set default BaudRate Supported from 0 - default to 6000000 @@ -339,9 +344,9 @@ typedef struct { **/ UINT8 SerialIoUartAutoFlow[7]; -/** Offset 0x0152 - Reserved +/** Offset 0x0152 **/ - UINT8 Reserved5[2]; + UINT8 UnusedUpdSpace5[2]; /** Offset 0x0154 - SerialIoUartRtsPinMuxPolicy Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* @@ -654,9 +659,19 @@ typedef struct { **/ UINT8 PchTsnLinkSpeed; -/** Offset 0x038F - Reserved +/** Offset 0x038F **/ - UINT8 Reserved6[9]; + UINT8 UnusedUpdSpace6; + +/** Offset 0x0390 - PCH TSN MAC Address High Bits + Set TSN MAC Address High. +**/ + UINT32 PchTsnMacAddressHigh; + +/** Offset 0x0394 - PCH TSN MAC Address Low Bits + Set TSN MAC Address Low. +**/ + UINT32 PchTsnMacAddressLow; /** Offset 0x0398 - PCIe PTM enable/disable Enable/disable Precision Time Measurement for PCIE Root Ports. @@ -680,9 +695,9 @@ typedef struct { **/ UINT8 UsbPdoProgramming; -/** Offset 0x03ED - Reserved +/** Offset 0x03ED **/ - UINT8 Reserved7[3]; + UINT8 UnusedUpdSpace7[3]; /** Offset 0x03F0 - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will @@ -733,9 +748,9 @@ typedef struct { **/ UINT8 PchFivrExtVnnRailSupportedVoltageStates; -/** Offset 0x03FD - Reserved +/** Offset 0x03FD **/ - UINT8 Reserved8; + UINT8 UnusedUpdSpace8; /** Offset 0x03FE - External Vnn Voltage Value that will be used in S0ix/Sx states Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420 @@ -795,9 +810,9 @@ typedef struct { **/ UINT8 PmcDbgMsgEn; -/** Offset 0x040B - Reserved +/** Offset 0x040B **/ - UINT8 Reserved9; + UINT8 UnusedUpdSpace9; /** Offset 0x040C - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer. @@ -844,9 +859,9 @@ typedef struct { **/ UINT8 PchSpiExtendedBiosDecodeRangeEnable; -/** Offset 0x041D - Reserved +/** Offset 0x041D **/ - UINT8 Reserved10[3]; + UINT8 UnusedUpdSpace10[3]; /** Offset 0x0420 - Extended BIOS Direct Read Decode Range base Bits of 31:16 of a memory address that'll be a base for Extended BIOS Direct Read Decode. @@ -858,9 +873,25 @@ typedef struct { **/ UINT32 PchSpiExtendedBiosDecodeRangeLimit; -/** Offset 0x0428 - Reserved +/** Offset 0x0428 - USB Audio Offload enable + Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default) + $EN_DIS **/ - UINT8 Reserved11[12]; + UINT8 PchXhciUaolEnable; + +/** Offset 0x0429 +**/ + UINT8 UnusedUpdSpace11[3]; + +/** Offset 0x042C - Pointer of SYNPS PHY Binary + ChipsetInit Binary Pointer. +**/ + UINT32 SynpsPhyBinPtr; + +/** Offset 0x0430 - Length of SYNPS PHY Binary + ChipsetInit Binary Length. +**/ + UINT32 SynpsPhyBinLen; /** Offset 0x0434 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] @@ -989,9 +1020,9 @@ typedef struct { **/ UINT8 AmtSolEnabled; -/** Offset 0x0455 - Reserved +/** Offset 0x0455 **/ - UINT8 Reserved12; + UINT8 UnusedUpdSpace12; /** Offset 0x0456 - OS Timer 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0. @@ -1025,9 +1056,9 @@ typedef struct { **/ UINT8 PcieRpEnableCpm[28]; -/** Offset 0x04AF - Reserved +/** Offset 0x04AF **/ - UINT8 Reserved13; + UINT8 UnusedUpdSpace13[1]; /** Offset 0x04B0 - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to @@ -1136,9 +1167,27 @@ typedef struct { **/ UINT8 LidStatus; -/** Offset 0x0521 - Reserved +/** Offset 0x0521 - Set Iom stay in TC cold seconds in TCSS + Set Iom stay in TC cold seconds in IOM **/ - UINT8 Reserved14[8]; + UINT8 IomStayInTCColdSeconds; + +/** Offset 0x0522 - Set Iom before entering TC cold seconds in TCSS + Set Iom before entering TC cold seconds in IOM +**/ + UINT8 IomBeforeEnteringTCColdSeconds; + +/** Offset 0x0523 - SaPostMemRsvd + Reserved for PCH Post-Mem + $EN_DIS +**/ + UINT8 SaPostMemRsvd[5]; + +/** Offset 0x0528 - PCH xHCI enable HS Interrupt IN Alarm + PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled + $EN_DIS +**/ + UINT8 PchXhciHsiiEnable; /** Offset 0x0529 - Enable VMD controller Enable/disable to VMD controller.0: Disable; 1: Enable(Default) @@ -1195,9 +1244,9 @@ typedef struct { **/ UINT8 VmdMemBar2Attr; -/** Offset 0x058D - Reserved +/** Offset 0x058D **/ - UINT8 Reserved15[3]; + UINT8 UnusedUpdSpace14[3]; /** Offset 0x0590 - VMD Variable VMD Variable Pointer. @@ -1219,9 +1268,12 @@ typedef struct { **/ UINT32 VmdMemBar2Base; -/** Offset 0x05A0 - Reserved +/** Offset 0x05A0 - TCSS CPU USB PDO Programming + Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow + for programming during later phase. 1: enable, 0: disable + $EN_DIS **/ - UINT8 Reserved16; + UINT8 TcssCpuUsbPdoProgramming; /** Offset 0x05A1 - Enable/Disable PMC-PD Solution This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution @@ -1274,18 +1326,20 @@ typedef struct { **/ UINT8 VccSt; -/** Offset 0x05B1 - Reserved +/** Offset 0x05B1 **/ - UINT8 Reserved17; + UINT8 UnusedUpdSpace15[1]; /** Offset 0x05B2 - ITBT DMA LTR TCSS DMA1, DMA2 LTR value **/ UINT16 ITbtDmaLtr[2]; -/** Offset 0x05B6 - Reserved +/** Offset 0x05B6 - Enable/Disable CrashLog + Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + $EN_DIS **/ - UINT8 Reserved18; + UINT8 CpuCrashLogEnable; /** Offset 0x05B7 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -1308,9 +1362,9 @@ typedef struct { **/ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; -/** Offset 0x05C7 - Reserved +/** Offset 0x05C7 **/ - UINT8 Reserved19; + UINT8 UnusedUpdSpace16[1]; /** Offset 0x05C8 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. @@ -1360,9 +1414,9 @@ typedef struct { **/ UINT8 Psi4Enable[5]; -/** Offset 0x05F3 - Reserved +/** Offset 0x05F3 **/ - UINT8 Reserved20; + UINT8 UnusedUpdSpace17[1]; /** Offset 0x05F4 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. @@ -1387,9 +1441,9 @@ typedef struct { **/ UINT8 TdcEnable[5]; -/** Offset 0x0612 - Reserved +/** Offset 0x0612 **/ - UINT8 Reserved21[2]; + UINT8 UnusedUpdSpace18[2]; /** Offset 0x0614 - Thermal Design Current time window PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. @@ -1436,9 +1490,9 @@ typedef struct { **/ UINT8 SlowSlewRate[5]; -/** Offset 0x063B - Reserved +/** Offset 0x063B **/ - UINT8 Reserved22; + UINT8 UnusedUpdSpace19[1]; /** Offset 0x063C - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. @@ -1505,9 +1559,9 @@ typedef struct { **/ UINT8 FivrSpreadSpectrum; -/** Offset 0x0687 - Reserved +/** Offset 0x0687 **/ - UINT8 Reserved23; + UINT8 UnusedUpdSpace20; /** Offset 0x0688 - CpuBistData Pointer CPU BIST Data @@ -1542,9 +1596,9 @@ typedef struct { **/ UINT8 RampDown; -/** Offset 0x0693 - Reserved +/** Offset 0x0693 **/ - UINT8 Reserved24; + UINT8 UnusedUpdSpace21[1]; /** Offset 0x0694 - VR Voltage Limit PCODE MMIO Mailbox: Voltage Limit. Range is 0 - 7999mV @@ -1557,9 +1611,40 @@ typedef struct { **/ UINT16 VccInAuxImonIccImax; -/** Offset 0x06A0 - Reserved +/** Offset 0x06A0 - Vsys Critical + PCODE MMIO Mailbox: Vsys Critical. 0: Disable; 1: Enable Range is 0-255. **/ - UINT8 Reserved25[7]; + UINT8 EnableVsysCritical; + +/** Offset 0x06A1 - Vsys Full Scale + DEPRECATED +**/ + UINT8 VsysFullScale; + +/** Offset 0x06A2 - Vsys Critical Threshold + DEPRECATED +**/ + UINT8 VsysCriticalThreshold; + +/** Offset 0x06A3 - Assertion Deglitch Mantissa + Assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchMantissa; + +/** Offset 0x06A4 - Assertion Deglitch Exponent + Assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysAssertionDeglitchExponent; + +/** Offset 0x06A5 - De assertion Deglitch Mantissa + De assertion Deglitch Mantissa, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchMantissa; + +/** Offset 0x06A6 - De assertion Deglitch Exponent + De assertion Deglitch Exponent, Range is 0-255 +**/ + UINT8 VsysDeassertionDeglitchExponent; /** Offset 0x06A7 - VccIn Aux Imon slope correction PCODE MMIO Mailbox: VccIn Aux Imon slope correction. 0 - Auto Specified in @@ -1567,18 +1652,30 @@ typedef struct { **/ UINT8 VccInAuxImonSlope; -/** Offset 0x06A8 - Reserved +/** Offset 0x06A8 - VccIn Aux Imon offset correction + PCODE MMIO Mailbox: VccIn Aux Imon offset correction. 0 - Auto Units 1/1000, + Range 0-63999. For an offset of 25.348, enter 25348. **/ - UINT8 Reserved26[2]; + UINT16 VccInAuxImonOffset; /** Offset 0x06AA - FIVR RFI Spread Spectrum Enable or disable Enable or Disable FIVR RFI Spread Spectrum. 0: Disable ; 1: Enable **/ UINT8 FivrSpectrumEnable; -/** Offset 0x06AB - Reserved +/** Offset 0x06AB **/ - UINT8 Reserved27[13]; + UINT8 UnusedUpdSpace22[1]; + +/** Offset 0x06AC - VR Fast Vmode ICC Limit support + PCODE MMIO Mailbox: The non-zero value will only be effective by setting the corresponding + EnableFastVmode to 1. 0-510A in 1/4 A units. 400 = 100A +**/ + UINT16 IccLimit[5]; + +/** Offset 0x06B6 +**/ + UINT8 CpuPostMemRsvd[2]; /** Offset 0x06B8 - PpinSupport to view Protected Processor Inventory Number Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this @@ -1599,9 +1696,17 @@ typedef struct { **/ UINT16 MinVoltageRuntime; -/** Offset 0x06BC - Reserved +/** Offset 0x06BC - Memory size per thread allocated for Processor Trace + Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment + and size in bytes per thread, from 4KB to 128MB.\n + 0xff:none , 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k, + 0x7:512k, 0x8:1M, 0x9:2M, 0xa:4M. 0xb:8M, 0xc:16M, 0xd:32M, 0xe:64M, 0xf:128M **/ - UINT8 Reserved28[2]; + UINT8 ProcessorTraceMemSize; + +/** Offset 0x06BD +**/ + UINT8 UnusedUpdSpace23; /** Offset 0x06BE - Min Voltage for C8 PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = @@ -1633,9 +1738,11 @@ typedef struct { **/ UINT8 Avx3Disable; -/** Offset 0x06C9 - Reserved +/** Offset 0x06C9 - X2ApicSupport + Enable or Disable X2APIC Support + $EN_DIS **/ - UINT8 Reserved29; + UINT8 X2ApicSupport; /** Offset 0x06CA - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. This value @@ -1644,9 +1751,38 @@ typedef struct { **/ UINT8 VrPowerDeliveryDesign; -/** Offset 0x06CB - Reserved +/** Offset 0x06CB - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; The value will only be effective by enabling the corresponding + CEP.0: Disable; 1: Enable.For all VR by domain + 0: Disable, 1: Enable **/ - UINT8 Reserved30[32]; + UINT8 EnableFastVmode[5]; + +/** Offset 0x06D0 - Vsys Full Scale + Vsys Full Scale, Range is 0-255000mV +**/ + UINT32 VsysFullScale1; + +/** Offset 0x06D4 - Vsys Critical Threshold + Vsys Critical Threshold, Range is 0-255000mV +**/ + UINT32 VsysCriticalThreshold1; + +/** Offset 0x06D8 - Psys Full Scale + Vsys Full Scale, Range is 0-255000mV +**/ + UINT32 PsysFullScale; + +/** Offset 0x06DC - Psys Critical Threshold + Vsys Critical Threshold, Range is 0-255000mV +**/ + UINT32 PsysCriticalThreshold; + +/** Offset 0x06E0 - ReservedCpuPostMemProduction + Reserved for CPU Post-Mem Production + $EN_DIS +**/ + UINT8 ReservedCpuPostMemProduction[11]; /** Offset 0x06EB - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. @@ -1838,9 +1974,12 @@ typedef struct { **/ UINT32 ThcPort0InterruptPinMuxing; -/** Offset 0x0894 - Reserved +/** Offset 0x0894 - Touch Host Controller Port 0 Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI + $EN_DIS **/ - UINT8 Reserved31; + UINT8 ThcPort0WakeOnTouch; /** Offset 0x0895 - Touch Host Controller Port 1 Assignment Assign THC Port 1 @@ -1848,9 +1987,10 @@ typedef struct { **/ UINT8 ThcPort1Assignment; -/** Offset 0x0896 - Reserved +/** Offset 0x0896 - Touch Host Controller Port 1 Hid Over Spi Reset Sequencing Delay [ms] + Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms **/ - UINT8 Reserved32[2]; + UINT16 ThcPort1HidResetSequencingDelay; /** Offset 0x0898 - Touch Host Controller Port 1 Interrupt Pin Mux Set THC Port 1 Pin Muxing Value if signal can be enabled on multiple pads. Refer @@ -1858,9 +1998,12 @@ typedef struct { **/ UINT32 ThcPort1InterruptPinMuxing; -/** Offset 0x089C - Reserved +/** Offset 0x089C - Touch Host Controller Port 1 Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI + $EN_DIS **/ - UINT8 Reserved33; + UINT8 ThcPort1WakeOnTouch; /** Offset 0x089D - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; @@ -1890,9 +2033,10 @@ typedef struct { **/ UINT8 PcieRpL1Substates[28]; -/** Offset 0x0929 - Reserved +/** Offset 0x0929 - PCIE RP L1 Low Substate + The L1 Low Substate configuration of the root port. 0: Disable; 1: Enable. **/ - UINT8 Reserved34[28]; + UINT8 PcieRpL1Low[28]; /** Offset 0x0945 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. @@ -1948,9 +2092,14 @@ typedef struct { **/ UINT8 PcieEqPh3PresetList[11]; -/** Offset 0x09A1 - Reserved +/** Offset 0x09A1 **/ - UINT8 Reserved35[3]; + UINT8 UnusedUpdSpace24; + +/** Offset 0x09A2 - Touch Host Controller Port 0 Hid Over Spi Reset Sequencing Delay [ms] + Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms +**/ + UINT16 ThcPort0HidResetSequencingDelay; /** Offset 0x09A4 - PCIe EQ phase 1 downstream transmitter port preset Allows to select the downstream port preset value that will be used during phase @@ -2226,8 +2375,7 @@ typedef struct { UINT8 SataRstPcieDeviceResetDelay[3]; /** Offset 0x0A42 - UFS enable/disable - Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller - 0 and (0,1) to enable controller 1 + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms $EN_DIS **/ UINT8 UfsEnable[2]; @@ -2238,9 +2386,9 @@ typedef struct { **/ UINT8 IehMode; -/** Offset 0x0A45 - Reserved +/** Offset 0x0A45 **/ - UINT8 Reserved36; + UINT8 UnusedUpdSpace25; /** Offset 0x0A46 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -2413,9 +2561,9 @@ typedef struct { **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x0A6B - Reserved +/** Offset 0x0A6B **/ - UINT8 Reserved37; + UINT8 UnusedUpdSpace26; /** Offset 0x0A6C - Thermal Device Temperature Decides the temperature. @@ -2438,9 +2586,14 @@ typedef struct { **/ UINT8 PchUsbLtrOverrideEnable; -/** Offset 0x0A89 - Reserved +/** Offset 0x0A89 - Touch Host Controller Mode + Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid **/ - UINT8 Reserved38[3]; + UINT8 ThcMode[2]; + +/** Offset 0x0A8B +**/ + UINT8 UnusedUpdSpace27; /** Offset 0x0A8C - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2488,9 +2641,26 @@ typedef struct { **/ UINT8 HybridStorageMode; -/** Offset 0x0A9C - Reserved +/** Offset 0x0A9C - CPU Root Port used for Hybrid Storage + Specifies the CPU root port used for Hybrid storage. **/ - UINT8 Reserved39[4]; + UINT8 CpuRootportUsedForHybridStorage; + +/** Offset 0x0A9D - PCH Root Port used for Hybrid Storage when two lanes are connected to CPU + Specifies PCH Root Port used for Hybrid Storage when two lanes are connected to CPU. +**/ + UINT8 PchRootportUsedForCpuAttach; + +/** Offset 0x0A9E - PCH GPE event handler + Enabled _L6D ACPI handler. PME GPE is shared by multiple devices So BIOS must verify + the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit + $EN_DIS +**/ + UINT8 PchAcpiL6dPmeHandling; + +/** Offset 0x0A9F +**/ + UINT8 UnusedUpdSpace28[1]; /** Offset 0x0AA0 - BgpdtHash[4] BgpdtHash values @@ -2502,9 +2672,9 @@ typedef struct { **/ UINT32 BiosGuardAttr; -/** Offset 0x0AC4 - Reserved +/** Offset 0x0AC4 **/ - UINT8 Reserved40[4]; + UINT8 UnusedUpdSpace29[4]; /** Offset 0x0AC8 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2535,9 +2705,9 @@ typedef struct { **/ UINT8 SiSkipSsidProgramming; -/** Offset 0x0ADB - Reserved +/** Offset 0x0ADB **/ - UINT8 Reserved41; + UINT8 UnusedUpdSpace30; /** Offset 0x0ADC - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only @@ -2635,9 +2805,48 @@ typedef struct { **/ UINT8 PchPmLatchEventsC10Exit; -/** Offset 0x0B00 - Reserved +/** Offset 0x0B00 - PMC ADR enable + Enable/disable asynchronous DRAM refresh + $EN_DIS **/ - UINT8 Reserved42[12]; + UINT8 PmcAdrEn; + +/** Offset 0x0B01 - PMC ADR timer configuration enable + Enable/disable ADR timer configuration + $EN_DIS +**/ + UINT8 PmcAdrTimerEn; + +/** Offset 0x0B02 - PMC ADR phase 1 timer value + Enable/disable ADR timer configuration +**/ + UINT8 PmcAdrTimer1Val; + +/** Offset 0x0B03 - PMC ADR phase 1 timer multiplier value + Specify the multiplier value for phase 1 ADR timer +**/ + UINT8 PmcAdrMultiplier1Val; + +/** Offset 0x0B04 - PMC ADR host reset partition enable + Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message + $EN_DIS +**/ + UINT8 PmcAdrHostPartitionReset; + +/** Offset 0x0B05 - PMC ADR source select override enable + Tells the FSP to update the source select with platform value + $EN_DIS +**/ + UINT8 PmcAdrSrcOverride; + +/** Offset 0x0B06 +**/ + UINT8 UnusedUpdSpace31[2]; + +/** Offset 0x0B08 - PMC ADR source selection + Specify which sources should cause ADR flow +**/ + UINT32 PmcAdrSrcSel; /** Offset 0x0B0C - PCIE Eq Ph3 Lane Param Cm CPU_PCIE_EQ_LANE_PARAM. Coefficient C-1. @@ -2728,9 +2937,9 @@ typedef struct { **/ UINT8 CpuPcieSlotSelection; -/** Offset 0x0BD1 - Reserved +/** Offset 0x0BD1 **/ - UINT8 Reserved43[3]; + UINT8 UnusedUpdSpace32[3]; /** Offset 0x0BD4 - CPU PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This @@ -3005,9 +3214,9 @@ typedef struct { **/ UINT8 PchTsnMultiVcEnable; -/** Offset 0x0CA2 - Reserved +/** Offset 0x0CA2 **/ - UINT8 Reserved44[2]; + UINT8 UnusedUpdSpace33[2]; /** Offset 0x0CA4 - LogoPixelHeight Address Address of LogoPixelHeight @@ -3024,9 +3233,17 @@ typedef struct { **/ UINT8 Usb4CmMode; -/** Offset 0x0CAD - Reserved +/** Offset 0x0CAD - PCIE Resizable BAR Support + Enable/Disable PCIE Resizable BAR Support.0: Disable; 1: Enable; 2: Auto(Default). + $EN_DIS **/ - UINT8 Reserved45[4]; + UINT8 CpuPcieResizableBarSupport; + +/** Offset 0x0CAE - SaPostMemTestRsvd + Reserved for SA Post-Mem Test + $EN_DIS +**/ + UINT8 SaPostMemTestRsvd[3]; /** Offset 0x0CB1 - RSR feature Enable or Disable RSR feature; 0: Disable; 1: Enable @@ -3034,9 +3251,11 @@ typedef struct { **/ UINT8 EnableRsr; -/** Offset 0x0CB2 - Reserved +/** Offset 0x0CB2 - ReservedCpuPostMem1 + Reserved for CPU Post-Mem 1 + $EN_DIS **/ - UINT8 Reserved46[4]; + UINT8 ReservedCpuPostMem1[4]; /** Offset 0x0CB6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; @@ -3427,9 +3646,9 @@ typedef struct { **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0D2D - Reserved +/** Offset 0x0D2D **/ - UINT8 Reserved47; + UINT8 UnusedUpdSpace34; /** Offset 0x0D2E - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. @@ -3467,9 +3686,9 @@ typedef struct { **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0D3A - Reserved +/** Offset 0x0D3A **/ - UINT8 Reserved48[2]; + UINT8 UnusedUpdSpace35[2]; /** Offset 0x0D3C - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. @@ -3570,9 +3789,11 @@ typedef struct { **/ UINT8 HwpInterruptControl; -/** Offset 0x0D73 - Reserved +/** Offset 0x0D73 - ReservedCpuPostMem2 + Reserved for CPU Post-Mem 2 + $EN_DIS **/ - UINT8 Reserved49[4]; + UINT8 ReservedCpuPostMem2[4]; /** Offset 0x0D77 - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled @@ -3642,9 +3863,11 @@ typedef struct { **/ UINT8 ApplyConfigTdp; -/** Offset 0x0D82 - Reserved +/** Offset 0x0D82 - Misc Power Management MSR Lock + Lock Misc Power Management MSR. Enable/Disable; 0: Disable , 1: Enable + $EN_DIS **/ - UINT8 Reserved50; + UINT8 HwpLock; /** Offset 0x0D83 - Dual Tau Boost Enable, Disable Dual Tau Boost feature. This is only applicable for Desktop; 0: @@ -3653,9 +3876,33 @@ typedef struct { **/ UINT8 DualTauBoost; -/** Offset 0x0D84 - Reserved +/** Offset 0x0D84 - Is Battery Present + BatteryPresent Enable/Disable; 0: Disable ; 1:Enable + $EN_DIS **/ - UINT8 Reserved51[32]; + UINT8 StepDownMode; + +/** Offset 0x0D85 - Platform ATX Telemetry Unit + Set ATX Telemetry Unit in Watts or Percentage; 0: Watts; 1: Percent +**/ + UINT8 PlatformAtxTelemetryUnit; + +/** Offset 0x0D86 - ProcHot Demotion Algorithm configuration + ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable; + 1: Hardware Default + $EN_DIS +**/ + UINT8 ProcHotDemotion; + +/** Offset 0x0D87 - ReservedCpuPostMemTest + Reserved for CPU Post-Mem Test + $EN_DIS +**/ + UINT8 ReservedCpuPostMemTest[13]; + +/** Offset 0x0D94 +**/ + UINT8 SecurityPostMemRsvd[16]; /** Offset 0x0DA4 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3702,9 +3949,9 @@ typedef struct { **/ UINT8 PchSbAccessUnlock; -/** Offset 0x0DAB - Reserved +/** Offset 0x0DAB **/ - UINT8 Reserved52; + UINT8 UnusedUpdSpace36[1]; /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -3854,12 +4101,18 @@ typedef struct { **/ UINT8 CpuPcieRpGen4Dptp[4]; -/** Offset 0x0F96 - Reserved +/** Offset 0x0F96 - PCIE RP Upstream Port Transmiter Preset + Used during Gen5 Link Equalization. Used for all lanes. Default is 7. **/ - UINT8 Reserved53[8]; + UINT8 CpuPcieRpGen5Uptp[4]; -/** Offset 0x0F9E - Type C Port x Convert to Type A - Enable / Disable (default) Type C Port x Convert to Type A +/** Offset 0x0F9A - PCIE RP Downstream Port Transmiter Preset + Used during Gen5 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 CpuPcieRpGen5Dptp[4]; + +/** Offset 0x0F9E - Type C Port x Convert to TypeA + Enable / Disable(default) Type C Port x Convert to TypeA $EN_DIS **/ UINT8 EnableTcssCovTypeA[4]; @@ -3887,9 +4140,33 @@ typedef struct { **/ UINT8 CpuPcieRpPeerToPeerMode[4]; -/** Offset 0x0FAF - Reserved +/** Offset 0x0FAF - Turbo Ratio Limit Ratio array + TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine + the active core ranges for each frequency point. **/ - UINT8 Reserved54[33]; + UINT8 TurboRatioLimitRatio[8]; + +/** Offset 0x0FB7 - Turbo Ratio Limit Num Core array + TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine + the active core ranges for each frequency point. +**/ + UINT8 TurboRatioLimitNumCore[8]; + +/** Offset 0x0FBF - ATOM Turbo Ratio Limit Ratio array + AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to + determine the active core ranges for each frequency point. +**/ + UINT8 AtomTurboRatioLimitRatio[8]; + +/** Offset 0x0FC7 - ATOM Turbo Ratio Limit Num Core array + AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to + determine the active core ranges for each frequency point. +**/ + UINT8 AtomTurboRatioLimitNumCore[8]; + +/** Offset 0x0FCF +**/ + UINT8 UnusedUpdSpace37; /** Offset 0x0FD0 - FspEventHandler Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. @@ -3914,9 +4191,9 @@ typedef struct { **/ UINT8 EmmcUseCustomDlls; -/** Offset 0x0FD7 - Reserved +/** Offset 0x0FD7 **/ - UINT8 Reserved55; + UINT8 UnusedUpdSpace38; /** Offset 0x0FD8 - Emmc Tx CMD Delay control register value Please see Tx CMD Delay Control register definition for help @@ -3948,9 +4225,73 @@ typedef struct { **/ UINT32 EmmcRxStrobeDelayRegValue; -/** Offset 0x0FF0 - Reserved +/** Offset 0x0FF0 - Emmc Command Pin Mux + Select pin muxing. Refer to GPIO_*_MUXING_EMMC_CMD* for possible values. **/ - UINT8 Reserved56[69]; + UINT32 EmmcGpioCmdPinMux; + +/** Offset 0x0FF4 - Emmc Command Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioCmdPadTermination; + +/** Offset 0x0FF5 - Emmc Data Pin Mux + Select pin muxing. Refer to GPIO_*_MUXING_EMMC_DATA_x* for possible values. One + UINT32 for each data pin [0-8] +**/ + UINT8 EmmcGpioDataPinMux[32]; + +/** Offset 0x1015 - Emmc Data Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up. One byte for each data pin [0-8] +**/ + UINT8 EmmcGpioDataPadTermination[8]; + +/** Offset 0x101D +**/ + UINT8 UnusedUpdSpace39[3]; + +/** Offset 0x1020 - Emmc Rclk PinMux + Select Rclk pin muxing. Refer to GPIO_*_MUXING_EMMC_RCLK* for possible values. +**/ + UINT32 EmmcGpioRclkPinMux; + +/** Offset 0x1024 - Emmc Rclk Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioRclkPadTermination; + +/** Offset 0x1025 +**/ + UINT8 UnusedUpdSpace40[3]; + +/** Offset 0x1028 - Emmc Clock Pin Mux + Select Clock pin muxing. Refer to GPIO_*_MUXING_EMMC_CLK* for possible values. +**/ + UINT32 EmmcGpioClkPinMux; + +/** Offset 0x102C - Emmc Clock Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioClkPadTermination; + +/** Offset 0x102D +**/ + UINT8 UnusedUpdSpace41[3]; + +/** Offset 0x1030 - Emmc Resetb PinMux + Select Resetb pin muxing. Refer to GPIO_*_MUXING_EMMC_RESETB* for possible values. +**/ + UINT32 EmmcGpioResetbPinMux; + +/** Offset 0x1034 - Emmc Resetb Pad Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up +**/ + UINT8 EmmcGpioResetbPadTermination; /** Offset 0x1035 - Enable VMD Global Mapping Enable/disable to VMD controller.0: Disable; 1: Enable(Default) @@ -3958,9 +4299,125 @@ typedef struct { **/ UINT8 VmdGlobalMapping; -/** Offset 0x1036 - Reserved +/** Offset 0x1036 - CPU PCIE Port0 Link Disable + CPU PCIE Port0 Link Disable while Device attached into Port0 and Port1.0: Disable(Default); + 1: Enable. + $EN_DIS **/ - UINT8 Reserved57[138]; + UINT8 CpuPcieFunc0LinkDisable[4]; + +/** Offset 0x103A - Skip VccIn Configuration + Skips VccIn configuration when enabled + $EN_DIS +**/ + UINT8 PmcSkipVccInConfig; + +/** Offset 0x103B - CSE Data Resilience Support + 0: Disable CSE Data Resilience Support. ; 1: Enable CSE Data Resilience Support. + $EN_DIS +**/ + UINT8 CseDataResilience; + +/** Offset 0x103C - HorizontalResolution for PEI Logo + HorizontalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 HorizontalResolution; + +/** Offset 0x1040 - VerticalResolution for PEI Logo + VerticalResolution from PEIm Gfx for PEI Logo +**/ + UINT32 VerticalResolution; + +/** Offset 0x1044 - Touch Host Controller Active Ltr + Expose Active Ltr for OS driver to set +**/ + UINT32 ThcActiveLtr[2]; + +/** Offset 0x104C - Touch Host Controller Idle Ltr + Expose Idle Ltr for OS driver to set +**/ + UINT32 ThcIdleLtr[2]; + +/** Offset 0x1054 - Touch Host Controller Hid Over Spi ResetPad + Hid Over Spi ResetPad 0x0 - Use THC HW default Pad, For other pad setting refer + to GpioPins +**/ + UINT32 ThcHidResetPad[2]; + +/** Offset 0x105C - Touch Host Controller Hid Over Spi ResetPad Trigger + Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High +**/ + UINT32 ThcHidResetPadTrigger[2]; + +/** Offset 0x1064 - Touch Host Controller Hid Over Spi Connection Speed + Hid Over Spi Connection Speed - SPI Frequency +**/ + UINT32 ThcHidConnectionSpeed[2]; + +/** Offset 0x106C - Touch Host Controller Hid Over Spi Limit PacketSize + When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc + packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes +**/ + UINT32 ThcLimitPacketSize[2]; + +/** Offset 0x1074 - Touch Host Controller Hid Over Spi Limit PacketSize + Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation + and begin of read operation. This value shall be in 10us multiples 0x0: Disabled, + 1-65535 (0xFFFF) - up to 655350 us +**/ + UINT32 ThcPerformanceLimitation[2]; + +/** Offset 0x107C - Touch Host Controller Hid Over Spi Input Report Header Address + Hid Over Spi Input Report Header Address +**/ + UINT32 ThcHidInputReportHeaderAddress[2]; + +/** Offset 0x1084 - Touch Host Controller Hid Over Spi Input Report Body Address + Hid Over Spi Input Report Body Address +**/ + UINT32 ThcHidInputReportBodyAddress[2]; + +/** Offset 0x108C - Touch Host Controller Hid Over Spi Output Report Address + Hid Over Spi Output Report Address +**/ + UINT32 ThcHidOutputReportAddress[2]; + +/** Offset 0x1094 - Touch Host Controller Hid Over Spi Read Opcode + Hid Over Spi Read Opcode +**/ + UINT32 ThcHidReadOpcode[2]; + +/** Offset 0x109C - Touch Host Controller Hid Over Spi Write Opcode + Hid Over Spi Write Opcode +**/ + UINT32 ThcHidWriteOpcode[2]; + +/** Offset 0x10A4 - Touch Host Controller Hid Over Spi Flags + Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode +**/ + UINT32 ThcHidFlags[2]; + +/** Offset 0x10AC +**/ + UINT8 UnusedUpdSpace42[4]; + +/** Offset 0x10B0 - MemoryBuffer + MemoryBuffer address +**/ + UINT64 MemoryBuffer; + +/** Offset 0x10B8 - MemorySize + MemorySize value +**/ + UINT32 MemorySize; + +/** Offset 0x10BC +**/ + UINT8 UnusedUpdSpace43[2]; + +/** Offset 0x10BE +**/ + UINT8 ReservedFspsUpd[2]; } FSP_S_CONFIG; /** Fsp S UPD Configuration