From eabe3957782b232e357c8ba60a559beafb2bedcf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 15 Apr 2025 17:12:12 +0530 Subject: [PATCH] soc/intel/fatcat: Override FSP-M UART MMIO for GFX PEIM debug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch overrides the FSP-M UART MMIO base address to ensure the FSP GFX PEIM can output debug console messages when required. Currently, the default UART MMIO base used by FSP-M/S might not be the intended console UART for debug output in boot stages, particularly for the GFX PEIM. By overriding it with the value derived from `CONFIG_UART_FOR_CONSOLE` when either `PcdSerialDebugLevel` or `SerialDebugMrcLevel` is non-zero, we ensure that debug logs are directed to the configured console. This change is crucial for debugging issues within the GFX PEIM initialization process. BUG=b:380375181 TEST=Verified that enabling FSP debug tokens after this change allows viewing debug output from the GFX PEIM during display initialization. Steps to reproduce: 1. Flash an AP FW image (`image.fatcat.serial.bin`). 2. Observe the absence of debug output from the GFX PEIM during display initialization. 3. Dynamically enable the FSP debug token using ``` sudo cbfstool image-fatcat.serial.bin add-int -i 3 -n option/fsp_pcd_debug_level ``` 4. Flash the modified AP FW image. 5. Observe debug output from the GFX PEIM during display initialization ``` [INFO]:[IsGraphicsDeviceSupported()]... [INFO]:[GetVbtStartAddress()] ``` Change-Id: I835ef75cb3046217127823c92f708bfe4f3ff741 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/87318 Reviewed-by: Kapil Porwal Reviewed-by: Jayvik Desai Tested-by: build bot (Jenkins) Reviewed-by: Alok Agarwal Reviewed-by: Jérémy Compostella --- src/soc/intel/pantherlake/romstage/fsp_params.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 521d2f2f09..b83eb18c7a 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -359,8 +359,11 @@ static void fsp_control_log_level(FSPM_UPD *mupd, bool is_enabled) } /* Set Event Handler if log-level is non-zero */ - if (m_cfg->PcdSerialDebugLevel || m_cfg->SerialDebugMrcLevel) + if (m_cfg->PcdSerialDebugLevel || m_cfg->SerialDebugMrcLevel) { arch_upd->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *)fsp_debug_event_handler); + /* Override SerialIo Uart default MMIO resource if log-level is non-zero */ + m_cfg->SerialIoUartDebugMmioBase = UART_BASE(CONFIG_UART_FOR_CONSOLE); + } } static void fill_fsp_event_handler(FSPM_UPD *mupd)