From ea81cb44a1c11cd78643c69ac818304cd393749e Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Thu, 24 Oct 2013 17:09:39 -0700 Subject: [PATCH] nyan: set up the aux channel i2c interface The AUX channel (panel communications link) is on i2c4. Enable the clocks for it. Not knowing any better, since no extant source or docs seem to indicate a best choice, we leave it on CLK_M, which is also the power on default. BUG=None TEST=Build and boot. Gets to depth charge. I've never see anything from depth charge so this is as far as I get. BRANCH=None Change-Id: I60882b9035ad901ddb3cf859a5e03558d918d989 Signed-off-by: Ronald G. Minnich Reviewed-on: https://chromium-review.googlesource.com/174620 Reviewed-by: Gabe Black Commit-Queue: Ronald Minnich Tested-by: Ronald Minnich --- src/mainboard/google/nyan/bootblock.c | 7 +++++++ src/soc/nvidia/tegra124/clock.c | 6 ++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index 49133ca55c..614f76ee6a 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -49,6 +49,12 @@ void bootblock_mainboard_init(void) // I2C3 (cam) data. pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C4 (DDC) clock. + pinmux_set_config(PINMUX_DDC_SCL_INDEX, + PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE); + // I2C4 (DDC) data. + pinmux_set_config(PINMUX_DDC_SDA_INDEX, + PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE); // I2C5 (PMU) clock. pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); @@ -59,6 +65,7 @@ void bootblock_mainboard_init(void) i2c_init(0); i2c_init(1); i2c_init(2); + i2c_init(3); i2c_init(4); pmic_init(4); diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 7656eebfd5..f1e34577de 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -338,7 +338,7 @@ void clock_config(void) CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); setbits_le32(&clk_rst->clk_out_enb_u, CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT | CLK_V_I2C4); setbits_le32(&clk_rst->clk_out_enb_w, CLK_W_DVFS); /* @@ -358,6 +358,8 @@ void clock_config(void) clock_ll_set_source_divisor(&clk_rst->clk_src_i2c2, 3, 16); /* I2C3 (cam) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 3, 16); + /* I2C4 (ddc) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 4, 16); /* I2C5 (PMU) gets CLK_M and a divisor of 17 */ clock_ll_set_source_divisor(&clk_rst->clk_src_i2c5, 3, 16); @@ -390,6 +392,6 @@ void clock_config(void) CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); clrbits_le32(&clk_rst->rst_dev_u, CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); - clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT); + clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT | CLK_V_I2C4); clrbits_le32(&clk_rst->rst_dev_w, CLK_W_DVFS); }