From e996d0bb05b8e977616b27711c9b41b2a181d749 Mon Sep 17 00:00:00 2001 From: Tom Zimmerman Date: Fri, 3 Oct 2003 15:43:26 +0000 Subject: [PATCH] Added PCI bus parity checking. An error will cause a NMI. Changed the x5dpr mptable to handle a pci card with a bridge on board. --- src/mainboard/supermicro/p4dpe/mainboard.c | 3 + src/mainboard/supermicro/p4dpr/mainboard.c | 3 + src/mainboard/supermicro/x5dpr/mainboard.c | 4 + src/mainboard/supermicro/x5dpr/mptable.c | 109 +++++++++++++++------ 4 files changed, 91 insertions(+), 28 deletions(-) diff --git a/src/mainboard/supermicro/p4dpe/mainboard.c b/src/mainboard/supermicro/p4dpe/mainboard.c index 8fa71517b4..e1e620a21c 100644 --- a/src/mainboard/supermicro/p4dpe/mainboard.c +++ b/src/mainboard/supermicro/p4dpe/mainboard.c @@ -82,6 +82,9 @@ void mainboard_fixup(void) isa_dma_init(); ich3_1e0_misc(); ich3_1f0_misc(); + e7500_pci_parity_enable(); + p64h2_pci_parity_enable(); + ich3_pci_parity_enable(); #if 0 /* CPU clock option is not presently used */ cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; diff --git a/src/mainboard/supermicro/p4dpr/mainboard.c b/src/mainboard/supermicro/p4dpr/mainboard.c index 8fa71517b4..0fd4239c95 100644 --- a/src/mainboard/supermicro/p4dpr/mainboard.c +++ b/src/mainboard/supermicro/p4dpr/mainboard.c @@ -82,6 +82,9 @@ void mainboard_fixup(void) isa_dma_init(); ich3_1e0_misc(); ich3_1f0_misc(); + e7500_pci_parity_enable(); + p64h2_pci_parity_enable(); + ich3_pci_parity_enable(); #if 0 /* CPU clock option is not presently used */ cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; diff --git a/src/mainboard/supermicro/x5dpr/mainboard.c b/src/mainboard/supermicro/x5dpr/mainboard.c index f9362956dd..e27f3abbfd 100644 --- a/src/mainboard/supermicro/x5dpr/mainboard.c +++ b/src/mainboard/supermicro/x5dpr/mainboard.c @@ -94,6 +94,10 @@ void mainboard_fixup(void) isa_dma_init(); ich3_1e0_misc(); ich3_1f0_misc(); + e7501_pci_parity_enable(); + p64h2_pci_parity_enable(); + ich3_pci_parity_enable(); + #if 0 /* CPU clock option is not presently used */ cpu_clock_multiplier = CPU_CLOCK_MULTIPLIER; diff --git a/src/mainboard/supermicro/x5dpr/mptable.c b/src/mainboard/supermicro/x5dpr/mptable.c index ef6e9b10b8..9c003868d1 100644 --- a/src/mainboard/supermicro/x5dpr/mptable.c +++ b/src/mainboard/supermicro/x5dpr/mptable.c @@ -10,6 +10,11 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) static const char oem[8] = "LNXI "; static const char productid[12] = "X5DPR "; struct mp_config_table *mc; + unsigned char bus_num; + unsigned char bus_isa; + unsigned char bus_0_1e; + unsigned char bus_1_1d; + unsigned char bus_1_1f; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); @@ -30,14 +35,48 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) smp_write_processors(mc, processor_map); - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "PCI "); - smp_write_bus(mc, 3, "PCI "); - smp_write_bus(mc, 4, "PCI "); - smp_write_bus(mc, 5, "ISA "); + { + struct pci_dev *dev; + uint32_t base; + /* 0:1e.0 */ + dev = pci_find_slot(0, PCI_DEVFN(0x1e,0)); + if (dev) { + pci_read_config_byte(dev, PCI_SECONDARY_BUS, &bus_0_1e); + pci_read_config_byte(dev, PCI_SUBORDINATE_BUS, &bus_isa); + bus_isa++; + } + else { + printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n"); + bus_0_1e = 4; + bus_isa = 5; + } + /* 1:1d.0 */ + dev = pci_find_slot(1, PCI_DEVFN(0x1d,0)); + if (dev) { + pci_read_config_byte(dev, PCI_SECONDARY_BUS, &bus_1_1d); + } + else { + printk_debug("ERROR - could not find PCI 1:1d.0, using defaults\n"); + bus_1_1d = 2; + } + /* 1:1f.0 */ + dev = pci_find_slot(1, PCI_DEVFN(0x1f,0)); + if (dev) { + pci_read_config_byte(dev, PCI_SECONDARY_BUS, &bus_1_1f); + } + else { + printk_debug("ERROR - could not find PCI 1:1f.0, using defaults\n"); + bus_1_1f = 3; + } + } - /* FIXME better IOAPIC handling */ + /* define bus and isa numbers */ + for(bus_num = 0; bus_num < bus_isa; bus_num++) { + smp_write_bus(mc, bus_num, "PCI "); + } + smp_write_bus(mc, bus_isa, "ISA "); + + /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x20, 0xfec00000); { @@ -61,25 +100,25 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x00, 0x02, 0x00); + bus_isa, 0x00, 0x02, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x01, 0x02, 0x01); + bus_isa, 0x01, 0x02, 0x01); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x00, 0x02, 0x02); + bus_isa, 0x00, 0x02, 0x02); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x03, 0x02, 0x03); + bus_isa, 0x03, 0x02, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x04, 0x02, 0x04); + bus_isa, 0x04, 0x02, 0x04); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x05, 0x02, 0x05); + bus_isa, 0x05, 0x02, 0x05); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x06, 0x02, 0x06); + bus_isa, 0x06, 0x02, 0x06); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x07, 0x02, 0x07); + bus_isa, 0x07, 0x02, 0x07); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x08, 0x02, 0x08); + bus_isa, 0x08, 0x02, 0x08); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x09, 0x02, 0x09); + bus_isa, 0x09, 0x02, 0x09); /* USB Controller */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, @@ -88,13 +127,13 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) 0x00, (0x1d<<2)|0, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x06, 0x0c, 0x02, 0x0c); + bus_isa, 0x0c, 0x02, 0x0c); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x0d, 0x02, 0x0d); + bus_isa, 0x0d, 0x02, 0x0d); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x0e, 0x02, 0x0e); + bus_isa, 0x0e, 0x02, 0x0e); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x0f, 0x02, 0x0f); + bus_isa, 0x0f, 0x02, 0x0f); /* USB Controller */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, @@ -108,25 +147,39 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) /* PCI slot 1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, (1<<2)|0, 0x03, 0x00); + bus_1_1f, (1<<2)|0, 0x03, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x03, (1<<2)|1, 0x03, 0x01); + bus_1_1f, (1<<2)|1, 0x03, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_1_1f, (1<<2)|2, 0x03, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_1_1f, (1<<2)|3, 0x03, 0x03); /* Slot 2 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x02, (1<<2)|0, 0x04, 0x00); + bus_1_1d, (1<<2)|0, 0x04, 0x00); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x02, (1<<2)|1, 0x04, 0x01); + bus_1_1d, (1<<2)|1, 0x04, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_1_1d, (1<<2)|2, 0x04, 0x02); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_1_1d, (1<<2)|3, 0x04, 0x03); + + /* SCSI */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_1_1f, (2<<2)|0, 0x03, 0x04); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + bus_1_1f, (2<<2)|1, 0x03, 0x05); /* VGA */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0x04, (1<<2)|0, 0x02, 0x10); + bus_0_1e, (1<<2)|0, 0x02, 0x10); /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x00, MP_APIC_ALL, 0x00); + bus_isa, 0x00, MP_APIC_ALL, 0x00); smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, - 0x05, 0x00, MP_APIC_ALL, 0x01); + bus_isa, 0x00, MP_APIC_ALL, 0x01); /* There is no extension information... */