These changes will, once they are used, allow the smm.elf to be generated.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1061 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
3490a5dd27
commit
e876fe3b3f
3 changed files with 63 additions and 20 deletions
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@ -55,4 +55,25 @@ STAGE0_CHIPSET_SRC += \
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$(src)/southbridge/intel/i82801gx/stage1_smbus.c \
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$(src)/southbridge/intel/i82801gx/libsmbus.c \
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$(obj)/southbridge/intel/i82801gx/smmhandler.o: $(src)/southbridge/intel/i82801gx/smmhandler.S
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -E $(COREBOOTINCLUDE) -I$(src)/northbridge/intel/i945 $< \
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-o $(obj)/southbridge/intel/i82801gx/smmhandler.s
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/southbridge/intel/i82801gx/smmhandler.s -o $@
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SMMSRC=$(src)/southbridge/intel/i82801gx/smihandler.c
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SMMOBJ := $(obj)/southbridge/intel/i82801gx/smihandler.o \
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$(obj)/lib/vtxprintf.o \
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$(obj)/lib/string.o \
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$(obj)/lib/mem.o \
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$(obj)/southbridge/intel/i82801gx/smmhandler.o
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$(obj)/southbridge/intel/i82801gx/smm.elf:$(src)/southbridge/intel/i82801gx/smm.ld \
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$(SMMOBJ)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -nostdlib -static -T $< -o $@ $(SMMOBJ)
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endif
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@ -19,15 +19,17 @@
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* MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/smm.h>
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#include "chip.h"
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#include <mainboard.h>
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#include <device/pci_def.h>
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#include <io.h>
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#include <console.h>
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#include <cpu.h>
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#include <smm.h>
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#include <stdarg.h>
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// Future TODO: Move to i82801gx directory
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#include "../../../northbridge/intel/i945/ich7.h"
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#include "../../../northbridge/intel/i945/i945.h"
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#define DEBUG_SMI
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@ -293,6 +295,8 @@ static void dump_tco_status(u32 tco_sts)
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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int console_loglevel = BIOS_SPEW;
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static int uart_can_tx_byte(void)
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{
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return inb(TTYS0_BASE + UART_LSR) & 0x20;
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@ -323,18 +327,35 @@ void console_tx_flush(void)
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uart_wait_to_tx_byte();
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}
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void console_tx_byte(unsigned char byte)
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void console_tx_byte(unsigned char byte, void *arg)
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{
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if (byte == '\n')
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uart_tx_byte('\r');
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uart_tx_byte(byte);
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}
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int printk(int msg_level, const char *fmt, ...)
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{
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int vtxprintf(void (*tx_byte)(unsigned char byte, void *arg), void *arg, const char *fmt, va_list args);
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va_list args;
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int i = 0;
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if (msg_level > console_loglevel) {
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return 0;
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}
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va_start(args, fmt);
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i += vtxprintf(console_tx_byte, (void *)0, fmt, args);
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va_end(args);
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return i;
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}
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/* We are using PCIe accesses for now
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* 1. the chipset can do it
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* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
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*/
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#include "../../../northbridge/intel/i945/pcie_config.c"
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#include "../../../northbridge/intel/i945/pcie_config.h"
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/* ********************* smi_util ************************* */
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@ -405,11 +426,10 @@ void smi_handler(u32 smm_revision)
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node=nodeid();
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#ifdef DEBUG_SMI
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console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
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console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
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#else
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console_loglevel = 1;
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#endif
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printk(BIOS_DEBUG, "\nSMI# #%d\n", node);
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switch (smm_revision) {
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@ -432,7 +452,7 @@ void smi_handler(u32 smm_revision)
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return;
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}
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pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
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pmbase = pcie_read_config16(PCI_BDF(0, 0x1f, 0), 0x40) & 0xfffc;
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printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase);
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/* We need to clear the SMI status registers, or we won't see what's
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@ -443,15 +463,17 @@ void smi_handler(u32 smm_revision)
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if (smi_sts & (1 << 21)) { // MONITOR
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global_nvs_t *gnvs = (global_nvs_t *)0xc00;
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int i;
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u32 reg32;
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reg32 = RCBA32(0x1e00); // TRSR - Trap Status Register
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#if 0
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/* Comment in for some useful debug */
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for (i=0; i<4; i++) {
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if (reg32 & (1 << i)) {
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printk(BIOS_DEBUG, " io trap #%d\n", i);
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{
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int i;
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/* Comment in for some useful debug */
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for (i=0; i<4; i++) {
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if (reg32 & (1 << i)) {
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printk(BIOS_DEBUG, " io trap #%d\n", i);
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}
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}
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}
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#endif
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@ -484,7 +506,7 @@ void smi_handler(u32 smm_revision)
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if (tco_sts & (1 << 8)) { // BIOSWR
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u8 bios_cntl;
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bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
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bios_cntl = pcie_read_config16(PCI_BDF(0, 0x1f, 0), 0xdc);
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if (bios_cntl & 1) {
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/* BWE is RW, so the SMI was caused by a
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@ -498,7 +520,7 @@ void smi_handler(u32 smm_revision)
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* box.
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*/
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printk(BIOS_DEBUG, "Switching back to RO\n");
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pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
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pcie_write_config32(PCI_BDF(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
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} /* No else for now? */
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}
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}
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@ -536,7 +558,7 @@ void smi_handler(u32 smm_revision)
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if (smi_sts & (1 << 4)) { // SLP_SMI
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u32 reg32;
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reg32 = inl(pmbase + 0x04);
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printk(BIOS_DEBUG, "SMI#: SLP = 0x%08x\n");
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printk(BIOS_DEBUG, "SMI#: SLP = 0x%08x\n", reg32);
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printk(BIOS_DEBUG, "SMI#: Powering off.\n");
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outl((6 << 10), pmbase + 0x04);
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outl((1 << 13) | (6 << 10), pmbase + 0x04);
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@ -52,7 +52,7 @@
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*
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*/
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#include <arch/asm.h>
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#define ASSEMBLY
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#define LAPIC_ID 0xfee00020
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