From e8599956dc87e72e7c318b789defead594061abf Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 25 Nov 2025 20:45:44 +0100 Subject: [PATCH] mb/amd/crater: Make NVMe reset GPIO configurable If you reworked the board its possible NVME reset is attached to GPIO 40 instead of 24. Signed-off-by: Maximilian Brune Change-Id: Ib2a10701ed2c3e677419f700a69277c2cde588f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90206 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/amd/crater/Kconfig | 6 ++++++ src/mainboard/amd/crater/early_gpio.c | 4 ++++ src/mainboard/amd/crater/gpio.c | 4 ++++ src/mainboard/amd/crater/port_descriptors_renoir.c | 2 ++ 4 files changed, 16 insertions(+) diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig index 729e1d6fd8..e8feffc94c 100644 --- a/src/mainboard/amd/crater/Kconfig +++ b/src/mainboard/amd/crater/Kconfig @@ -98,6 +98,12 @@ config ENABLE_M2_SSD help Use GPP[8:11] connected to M.2 SSD +config NVME_RST_GPIO40 + bool "NVMe Reset on GPIO40" + help + Select if the NVMe reset pin is connected to GPIO40. + Otherwise its assumed to be connected to GPIO24. + choice prompt "XGBE/WWAN/WLAN/DT Selection" default XGBE_WWAN_WLAN diff --git a/src/mainboard/amd/crater/early_gpio.c b/src/mainboard/amd/crater/early_gpio.c index 28ca462a39..de490b3ee1 100644 --- a/src/mainboard/amd/crater/early_gpio.c +++ b/src/mainboard/amd/crater/early_gpio.c @@ -26,7 +26,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = { /* PCIE_RST1_L */ PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), /* M2_SSD0_RST */ +#if CONFIG(NVME_RST_GPIO40) + PAD_GPO(GPIO_40, HIGH), +#else PAD_GPO(GPIO_24, HIGH), +#endif /* DEVSLP1 */ PAD_NFO(GPIO_6, DEVSLP1, LOW), diff --git a/src/mainboard/amd/crater/gpio.c b/src/mainboard/amd/crater/gpio.c index 27b045c245..b1da83e8db 100644 --- a/src/mainboard/amd/crater/gpio.c +++ b/src/mainboard/amd/crater/gpio.c @@ -28,7 +28,11 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = { /* PCIE_RST1_L */ PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), /* M2_SSD0_RST */ +#if CONFIG(NVME_RST_GPIO40) + PAD_GPO(GPIO_40, HIGH), +#else PAD_GPO(GPIO_24, HIGH), +#endif /* DEVSLP1 */ PAD_NFO(GPIO_6, DEVSLP1, LOW), diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c index 5ac965f84a..83e861d0ab 100644 --- a/src/mainboard/amd/crater/port_descriptors_renoir.c +++ b/src/mainboard/amd/crater/port_descriptors_renoir.c @@ -341,4 +341,6 @@ static void xgbe_init(FSP_M_CONFIG *mcfg) void mb_pre_fspm(FSP_M_CONFIG *mcfg) { xgbe_init(mcfg); + + mcfg->nvme_rst_gpio = CONFIG(NVME_RST_GPIO40) ? 40 : 24; }