UPSTREAM: src/include: Remove spaces before tabs
Fix the following warning detected by checkpatch.pl:
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: Ib41ee378b8ad74a0171b12e1cee7f24b6aa20905
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84d20d0eb3
Original-Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18652
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/453679
This commit is contained in:
Lee Leahy
chrome-bot
parent
fe76d4aaa9
commit
e7ff5b5fa4
16 changed files with 72 additions and 72 deletions
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@ -32,7 +32,7 @@
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/* GLCP_SYS_RSTPLL, Lower 32 bits */
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#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
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#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
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#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
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#define GLCP_SYS_RSTPLL_LOCKWAIT 24
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#define GLCP_SYS_RSTPLL_HOLDCOUNT 16
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#define GLCP_SYS_RSTPLL_BYPASS 15
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@ -456,9 +456,9 @@
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#define GLPCI_ARB_LOWER_VO2_SET (1 << 22)
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#define GLPCI_ARB_LOWER_OV1_SET (1 << 21)
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#define GLPCI_ARB_LOWER_OV0_SET (1 << 20)
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#define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
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#define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
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#define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
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#define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
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#define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
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#define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
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#define GLPCI_ARB_LOWER_CPRE_SET (1<<11)
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#define GLPCI_ARB_LOWER_PRE2_SET (1<<10)
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#define GLPCI_ARB_LOWER_PRE1_SET (1<<9)
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@ -35,20 +35,20 @@
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#define PCI_INT_CD 0x0A // GPIO pins for INTC# and INTD#
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#define WATCHDOG 0x0B // Watchdog timer
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#define MAX_MISC WATCHDOG
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#define MAX_MISC WATCHDOG
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// NOTE: Do not change the order of the following registers:
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#define VRC_AUDIO 0x01 // XpressAudio Class
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#define AUDIO_VERSION 0x00
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#define PM_STATE 0x01
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#define SB_16_IO_BASE 0x02
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#define MIDI_BASE 0x03
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#define CPU_USAGE 0x04
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#define CODEC_TYPE 0x05
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#define STATE_INDEX 0x06
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#define STATE_DATA 0x07
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#define AUDIO_IRQ 0x08 // For use by native audio drivers
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#define VRC_AUDIO 0x01 // XpressAudio Class
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#define AUDIO_VERSION 0x00
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#define PM_STATE 0x01
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#define SB_16_IO_BASE 0x02
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#define MIDI_BASE 0x03
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#define CPU_USAGE 0x04
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#define CODEC_TYPE 0x05
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#define STATE_INDEX 0x06
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#define STATE_DATA 0x07
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#define AUDIO_IRQ 0x08 // For use by native audio drivers
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#define STATUS_PTR 0x09 // For use by native audio drivers
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#define MAX_AUDIO STATUS_PTR
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@ -189,22 +189,22 @@
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// SAA7127 - Not Used
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// ADV7300 - HDTV resolutions only
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// LO -> 720x480p
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// MED -> 1280x720p
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// MED -> 1280x720p
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// HI -> 1920x1080i
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// FS454 - Both SD and HD resolutions
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// SD Resolutions - NTSC and PAL
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// FS454 - Both SD and HD resolutions
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// SD Resolutions - NTSC and PAL
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// LO -> 640x480
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// MED -> 800x600
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// MED -> 800x600
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// HI -> 1024x768
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// HD Resolutions
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// HD Resolutions
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// LO -> 720x480p
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// MED -> 1280x720p
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// MED -> 1280x720p
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// HI -> 1920x1080i
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#define VG_TV_RES 0x0780 // TV resolution select mask
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#define VG_TV_RES_SHIFT 0x0007 // Right shift value
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#define VG_TV_RES_LO 0x0000 // Low resolution
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#define VG_TV_RES_MED 0x0080 // Medium resolution
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#define VG_TV_RES_HI 0x0100 // High resolution
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#define VG_TV_RES_HI 0x0100 // High resolution
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#define VG_TV_PASSTHRU 0x0800 // TV passthru mode
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#define VG_TV_SCALE_ADJ 0x05 // Modifies scaling factors for TV resolutions
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@ -237,33 +237,33 @@
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#define VG_FT_VESST 0x2C // Fixed timings, vertical sync start
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#define VG_FT_VESND 0x2D // Fixed timings, vertical sync end
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#define MAX_VGA VGA_MEM_SIZE
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// #define MAX_VG VG_FP_OPTION
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// #define MAX_VG VG_START_OFFS_HI
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#define MAX_VG VG_FT_VESND
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#define MAX_VGA VGA_MEM_SIZE
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// #define MAX_VG VG_FP_OPTION
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// #define MAX_VG VG_START_OFFS_HI
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#define MAX_VG VG_FT_VESND
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#define VRC_APM 0x03
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#define REPORT_EVENT 0x00
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#define CAPABILITIES 0x01
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#define CAPABILITIES 0x01
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#define APM_PRESENT 0x02
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#define MAX_APM APM_PRESENT
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#define MAX_APM APM_PRESENT
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#define VRC_PM 0x04 // Legacy PM Class
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#define POWER_MODE 0x00
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#define POWER_STATE 0x01
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#define DOZE_TIMEOUT 0x02
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#define STANDBY_TIMEOUT 0x03
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#define SUSPEND_TIMEOUT 0x04
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#define STANDBY_TIMEOUT 0x03
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#define SUSPEND_TIMEOUT 0x04
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#define PS2_TIMEOUT 0x05
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#define RESUME_ON_RING 0x06
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#define VIDEO_TIMEOUT 0x07
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#define DISK_TIMEOUT 0x08
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#define FLOPPY_TIMEOUT 0x09
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#define FLOPPY_TIMEOUT 0x09
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#define SERIAL_TIMEOUT 0x0A
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#define PARALLEL_TIMEOUT 0x0B
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#define IRQ_WAKEUP_MASK 0x0C
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// #define SUSPEND_MODULATION 0x0D
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#define IRQ_WAKEUP_MASK 0x0C
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// #define SUSPEND_MODULATION 0x0D
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#define SLEEP_PIN 0x0E
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#define SLEEP_PIN_ATTR 0x0F
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// #define SMI_WAKEUP_MASK 0x10
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@ -308,24 +308,24 @@
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#define TV_CONTRAST 0x05
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#define TV_OUTPUT 0x06
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#define TV_TIMING 0x10 // 0x10...0x1D are all timings
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#define MAX_TV TV_TIMING
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#define MAX_TV TV_TIMING
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#define VRC_EXTERNAL_AMP 0x07
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#define EAPD_VERSION 0x00
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#define AMP_POWER 0x01
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#define AMP_POWER 0x01
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#define AMP_OFF 0x00
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#define AMP_ON 0x01
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#define AMP_TYPE 0x02
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#define MAX_EXTERNAL_AMP AMP_TYPE
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#define MAX_EXTERNAL_AMP AMP_TYPE
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#define VRC_ACPI 0x08
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#define ENABLE_ACPI 0x00 // Enable ACPI Mode
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#define SCI_IRQ 0x01 // Set the IRQ the SCI is mapped to, sysbios use.
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#define SCI_IRQ 0x01 // Set the IRQ the SCI is mapped to, sysbios use.
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#define ACPINVS_LO 0x02 // new calls to send 32bit physAddress of
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#define ACPINVS_HI 0x03 // ACPI NVS region to VSA
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#define ACPINVS_HI 0x03 // ACPI NVS region to VSA
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#define GLOBAL_LOCK 0x04 // read requests semaphore, write clears
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#define ACPI_UNUSED1 0x05
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#define RW_PIRQ 0x06 // read/write PCI IRQ router regs in SB Func0 cfg space
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@ -371,12 +371,12 @@
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#define MAX_KEYBOARD MOUSE_XY
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#define VRC_DDC 0x0D // Video DDC Class
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#define VRC_DDC_ENABLE 0x00 // Enable/disable register
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#define VRC_DDC 0x0D // Video DDC Class
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#define VRC_DDC_ENABLE 0x00 // Enable/disable register
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#define DDC_DISABLE 0x00
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#define DDC_ENABLE 0x01
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#define VRC_DDC_IO 0x01 // A non-zero value for safety
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#define MAX_DDC VRC_DDC_IO
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#define DDC_ENABLE 0x01
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#define VRC_DDC_IO 0x01 // A non-zero value for safety
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#define MAX_DDC VRC_DDC_IO
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#define VRC_DEBUGGER 0x0E
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#define MAX_DEBUGGER NO_VR
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@ -399,7 +399,7 @@
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#define VRC_OWL 0x11 // Virtual Register class
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#define VRC_OWL_DAC 0x00 // DAC (Backlight) Control
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#define VRC_OWL_GPIO 0x01 // GPIO Control
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#define VRC_OWL_GPIO 0x01 // GPIO Control
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#define MAX_OWL VRC_OWL_GPIO
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#define VRC_SYSINFO 0x12 // Virtual Register class
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@ -472,7 +472,7 @@
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#define VRC_THERMAL_SMB_DATA 0x09
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#define MAX_THERMAL VRC_THERMAL_SMB_DATA
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#define MAX_VR_CLASS VRC_THERMAL
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#define MAX_VR_CLASS VRC_THERMAL
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/*
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* Write to a Virtual Register
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@ -21,7 +21,7 @@
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#define LAPIC_RRR 0x0C0
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#define LAPIC_SVR 0x0f0
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#define LAPIC_SPIV 0x0f0
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#define LAPIC_SPIV_ENABLE 0x100
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#define LAPIC_SPIV_ENABLE 0x100
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#define LAPIC_ESR 0x280
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#define LAPIC_ESR_SEND_CS 0x00001
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#define LAPIC_ESR_RECV_CS 0x00002
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@ -30,7 +30,7 @@
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#define LAPIC_ESR_SENDILL 0x00020
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#define LAPIC_ESR_RECVILL 0x00040
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#define LAPIC_ESR_ILLREGA 0x00080
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#define LAPIC_ICR 0x300
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#define LAPIC_ICR 0x300
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#define LAPIC_DEST_SELF 0x40000
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#define LAPIC_DEST_ALLINC 0x80000
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#define LAPIC_DEST_ALLBUT 0xC0000
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@ -25,12 +25,12 @@
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#define SMRR_PHYS_BASE 0x1f2
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#define SMRR_PHYS_MASK 0x1f3
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#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
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#define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1)
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#define MTRR_PHYS_MASK_VALID (1 << 11)
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#define NUM_FIXED_RANGES 88
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#define RANGES_PER_FIXED_MTRR 8
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#define NUM_FIXED_RANGES 88
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#define RANGES_PER_FIXED_MTRR 8
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#define MTRR_FIX_64K_00000 0x250
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#define MTRR_FIX_16K_80000 0x258
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#define MTRR_FIX_16K_A0000 0x259
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