From e7cdf035fb565da370a4fb84d295df592d36a6b0 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Thu, 14 Aug 2025 14:33:55 +0800 Subject: [PATCH] mb/google/brox/var/caboc: Enable RTD3 for SSD to resolve S0ix issue Some SSDs block the CPU from reaching PC10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix. Enable and reset GPIOs are configured as per pin mapping in gpio.c. Disable GPP_F20 (EN_PP3300_SSD) and GPP_H23 (SRCCLKREQ#5) by fw_config for Non-SSD sku. BUG=b:435567235 TEST= emerge-brox coreboot suspend_stress_test verify that the device suspends to S0ix. suspend_stress_test w/o this CL (with Kioxia PCIE Gen4 SSD KBG60ZNV512G) Suspend failed, pc10 count did not increment from 0 Package C-States Now : Package C2 : 26205917 Package C3 : 0 Package C6 : 0 Package C7 : 0 Package C8 : 0 Package C9 : 0 Package C10 : 0 Substate Residency S0i2.0 0 S0i3.0 0 suspend_stress_test w/ this CL Device suspends to S0ix. Substate Residency S0i2.0 0 S0i3.0 12020538 Change-Id: Iecffa89ae7865bc63b1b0dd974a439f35e9ca7f4 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/88771 Reviewed-by: Wisley Chen Reviewed-by: sridhar siricilla Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Paul Menzel --- src/mainboard/google/brox/variants/caboc/fw_config.c | 4 ++++ src/mainboard/google/brox/variants/caboc/gpio.c | 4 ++++ src/mainboard/google/brox/variants/caboc/overridetree.cb | 7 +++++++ 3 files changed, 15 insertions(+) diff --git a/src/mainboard/google/brox/variants/caboc/fw_config.c b/src/mainboard/google/brox/variants/caboc/fw_config.c index 0f77546624..092c45ba69 100644 --- a/src/mainboard/google/brox/variants/caboc/fw_config.c +++ b/src/mainboard/google/brox/variants/caboc/fw_config.c @@ -49,8 +49,12 @@ static const struct pad_config lte_disable_pads[] = { static const struct pad_config nvme_disable_pads[] = { /* GPP_F9 : SSD_PERST_L */ PAD_NC(GPP_F9, NONE), + /* GPP_F20 : EN_PP3300_SSD */ + PAD_NC(GPP_F20, NONE), /* GPP_D5 : SSD_CLKREQ_ODL */ PAD_NC(GPP_D5, NONE), + /* GPP_H23 : SSD_CLKREQ5_ODL */ + PAD_NC(GPP_H23, NONE), }; static void fw_config_handle(void *unused) diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c index c13b80cc02..7a683eacc4 100644 --- a/src/mainboard/google/brox/variants/caboc/gpio.c +++ b/src/mainboard/google/brox/variants/caboc/gpio.c @@ -65,6 +65,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ_WWAN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F20, 1, DEEP), /* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/ PAD_CFG_GPO(GPP_F21, 1, DEEP), @@ -100,6 +102,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F20, 1, DEEP), /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb index e8be0e8990..575b865205 100644 --- a/src/mainboard/google/brox/variants/caboc/overridetree.cb +++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb @@ -251,6 +251,13 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER, .pcie_rp_aspm = ASPM_L1, }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F9)" + register "srcclk_pin" = "0" + device generic 0 on end + end probe STORAGE STORAGE_NVME probe unprovisioned end