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Various cosmetic fixes (trivial).

Browse source 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@143 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-02-27 13:58:07 +00:00
commit e6eb413ded
5 changed files with 12 additions and 13 deletions
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2
northbridge/intel/i440bxemulation/Kconfig
View file

@ -2,5 +2,5 @@ config NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE
int
default 32 # Mbytes
help
This is the default ram size of emulation
This is the default RAM size of emulation.

1
northbridge/intel/i440bxemulation/Makefile
View file

@ -24,6 +24,5 @@
$(obj)/i440bx.o: $(src)/northbridge/intel/i440bxemulation/i440bx.c
$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
STAGE2_CHIPSET_OBJ += $(obj)/i440bx.o

5
northbridge/intel/i440bxemulation/config.h
View file

@ -18,13 +18,12 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations northbridge_intel_i440bxemulation_ops;
struct northbridge_intel_i440bx_config
{
/* the various emulators don't always get 440bx right. So we are going to allow
* users to set the ramsize via Kconfig.
/* The various emulators don't always get 440BX right. So we are
* going to allow users to set the RAM size via Kconfig.
*/
int ramsize;
};

14
northbridge/intel/i440bxemulation/i440bx.c
View file

@ -27,12 +27,12 @@
#include "config.h"
#include "i440bx.h"
/* this is the starting point */
/* This is the starting point. */
static void i440bxemulation_enable_dev(struct device *dev)
{
printk(BIOS_INFO, "%s: \n", __FUNCTION__);
/* Set the operations if it is a special bus type */
/* Set the operations if it is a special bus type. */
/*
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
@ -46,18 +46,18 @@ struct chip_operations northbridge_intel_i440bxemulation_ops = {
.enable_dev = i440bxemulation_enable_dev,
};
/* here are the ops for 440bx as a pci domain */
/* Here are the ops for 440BX as a PCI domain. */
static void pci_domain_read_resources(struct device * dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
/* Initialize the system wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
/* Initialize the system wide memory resources constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
@ -81,7 +81,7 @@ static void ram_resource(struct device * dev, unsigned long index,
static void pci_domain_set_resources(struct device * dev)
{
struct device * mc_dev;
uint32_t tolmk; /* top of low mem, Kbytes */
uint32_t tolmk; /* Top of low mem, Kbytes. */
int idx;
struct northbridge_intel_i440bx_config *chip_info = dev->chip_info;
tolmk = chip_info->ramsize * 1024;
@ -105,4 +105,4 @@ struct device_operations i440bxemulation_pcidomainops = {
.phase5_enable_resources = enable_childrens_resources,
.phase6_init = 0,
.phase3_scan = pci_domain_scan_bus,
};
};

3
northbridge/intel/i440bxemulation/i440bx.h
View file

@ -87,4 +87,5 @@
#define PAM5 0x5e
#define PAM6 0x5f
unsigned int i440bx_scan_root_bus(struct device * root, unsigned int max);
unsigned int i440bx_scan_root_bus(struct device *root, unsigned int max);