erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: soc/intel/apollolake: Implement stage cache to improve resume time

Browse source 
This patch enables stage cache to save ~40ms during S3 resume.
It saves ramstage in the stage cache and restores it on resume
so that ramstage does not have to reinitialize during the
resume flow. Stage cache functionality is added to postcar stage
since ramstage is called from postcar.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for Reef and tested ramstage being cached

Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16833
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72
Reviewed-on: https://chromium-review.googlesource.com/396161
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brandon Breitenstein 2016-09-30 13:57:12 -07:00 • committed by chrome-bot
commit e6cd08ef53
8 changed files with 63 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/drivers/intel/fsp2_0/Makefile.inc
View file

@ -37,6 +37,8 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += util.c
postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
# Add FSP blobs into cbfs. SoC code may supply additional options with