From e6785d037dab1b5c1642142a411d44a73ff4e96a Mon Sep 17 00:00:00 2001
From: Jamie Ryu <jamie.m.ryu@intel.com>
Date: Tue, 29 Oct 2024 21:31:13 -0700
Subject: [PATCH] mb/google/fatcat: Enable s0ix

BUG=b:392235839
TEST=Build fatcat and boot to OS. Run suspend_stress_test to ensure
s0ix entry and exit working.

Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84923
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 .../google/fatcat/variants/baseboard/fatcat/devicetree.cb       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
index 92ea38d69f..342c534b7b 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
@@ -34,7 +34,7 @@ chip soc/intel/pantherlake
 	register "sagv" = "SAGV_ENABLED"
 
 	# Enable s0ix
-	register "s0ix_enable" = "false"
+	register "s0ix_enable" = "true"
 
 	# DPTF enable
 	register "dptf_enable" = "true"