From e5ade7cfb1eca79704b9ef7ab6dc9a2bce7eef62 Mon Sep 17 00:00:00 2001 From: Naresh Solanki Date: Wed, 2 Apr 2025 23:49:13 +0530 Subject: [PATCH] soc/amd/*/include/soc/msr.h: Move MSR to common location MSR definition in soc/amd/*/include/soc/msr.h are the same & hence move them to common header src/include/cpu/amd/msr.h Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d Signed-off-by: Naresh Solanki Reviewed-on: https://review.coreboot.org/c/coreboot/+/87124 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/include/cpu/amd/msr.h | 19 +++++++++++++++++++ src/soc/amd/cezanne/include/soc/msr.h | 20 ++------------------ src/soc/amd/genoa_poc/include/soc/msr.h | 22 ++-------------------- src/soc/amd/glinda/include/soc/msr.h | 20 ++------------------ src/soc/amd/mendocino/include/soc/msr.h | 20 ++------------------ src/soc/amd/phoenix/include/soc/msr.h | 20 ++------------------ 6 files changed, 29 insertions(+), 92 deletions(-) diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 3f7febc462..69425c5cca 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -78,4 +78,23 @@ #define CORE_PERF_BOOST_CTRL 0x15c +/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ +#define MSR_CPPC_CAPABILITY_1 0xc00102b0 +#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 +#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 +#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 +#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 + +#define MSR_CPPC_ENABLE 0xc00102b1 +#define MSR_CPPC_REQUEST 0xc00102b3 +#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 +#define SHIFT_CPPC_REQUEST_DES_PERF 16 +#define SHIFT_CPPC_REQUEST_MIN_PERF 8 +#define SHIFT_CPPC_REQUEST_MAX_PERF 0 + +#define MSR_CPPC_STATUS 0xc00102b4 + +#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 +#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 + #endif /* CPU_AMD_MSR_H */ diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 0fba3e6d83..1b7c98c1d2 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -3,6 +3,8 @@ #ifndef AMD_CEZANNE_MSR_H #define AMD_CEZANNE_MSR_H +#include + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -17,22 +19,4 @@ union pstate_msr { uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_CEZANNE_MSR_H */ diff --git a/src/soc/amd/genoa_poc/include/soc/msr.h b/src/soc/amd/genoa_poc/include/soc/msr.h index 31328ea994..6b0d0a8d34 100644 --- a/src/soc/amd/genoa_poc/include/soc/msr.h +++ b/src/soc/amd/genoa_poc/include/soc/msr.h @@ -3,6 +3,8 @@ #ifndef AMD_GENOA_POC_MSR_H #define AMD_GENOA_POC_MSR_H +#include + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -18,24 +20,4 @@ union pstate_msr { uint64_t raw; }; - -/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_GENOA_POC_MSR_H */ diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index 2f40d395f3..1c2a3c0be5 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -5,6 +5,8 @@ #ifndef AMD_GLINDA_MSR_H #define AMD_GLINDA_MSR_H +#include + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -20,22 +22,4 @@ union pstate_msr { uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_GLINDA_MSR_H */ diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index cfc7702c9f..ceb9bd9a6a 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -3,6 +3,8 @@ #ifndef AMD_MENDOCINO_MSR_H #define AMD_MENDOCINO_MSR_H +#include + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -18,22 +20,4 @@ union pstate_msr { uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_MENDOCINO_MSR_H */ diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h index 7acf3219b8..c81cdd289b 100644 --- a/src/soc/amd/phoenix/include/soc/msr.h +++ b/src/soc/amd/phoenix/include/soc/msr.h @@ -5,6 +5,8 @@ #ifndef AMD_PHOENIX_MSR_H #define AMD_PHOENIX_MSR_H +#include + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -20,22 +22,4 @@ union pstate_msr { uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_PHOENIX_MSR_H */