diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c index 7a509384b2..8f0000c2ce 100644 --- a/src/mainboard/google/fatcat/romstage.c +++ b/src/mainboard/google/fatcat/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include @@ -23,51 +22,6 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd) /* Nothing to do */ } -static bool soc_is_pantherlake_h(void) -{ - uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); - - if (mch_id == 0xffff) { - printk(BIOS_ERR, "No matching PCI DID present\n"); - return false; - } - - /* - * Identify Panther Lake H by testing all Memory Controller Hub (MCH) IDs utilized on fatcat - * devices. - */ - switch (mch_id) { - case PCI_DID_INTEL_PTL_H_ID_1: - case PCI_DID_INTEL_PTL_H_ID_2: - case PCI_DID_INTEL_PTL_H_ID_3: - case PCI_DID_INTEL_PTL_H_ID_4: - return true; - default: - return false; - } -} - -static void disable_vr_settings_on_pantherlake_h(FSP_M_CONFIG *m_cfg) -{ - if (!soc_is_pantherlake_h()) - return; - - /* - * The board operates a Panther Lake H SoC; disable the PTL-U VR settings. - * - * The Voltage Regulator (VR) configurations supplied by the device tree are - * specifically adjusted for a Panther Lake U SoC, which is intended for fatcat board - * designs. When these settings are applied to a board equipped with a Panther Lake H - * SoC, it may experience performance problems under high-stress conditions. This is - * because the I_TRIP value is set lower than the device's actual capability. - */ - printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n"); - for (size_t i = 0; i < NUM_VR_DOMAINS; i++) { - m_cfg->CepEnable[i] = false; - m_cfg->EnableFastVmode[i] = false; - } -} - void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; @@ -86,9 +40,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memcfg_init(memupd, mem_config, &spd_info, half_populated); - /* Override FSP-M Voltage Regulator settings on Panther Lake H. */ - disable_vr_settings_on_pantherlake_h(&memupd->FspmConfig); - /* Override FSP-M UPD per board if required. */ variant_update_soc_memory_init_params(memupd); } diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 6f04713ae3..00b4ea4506 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -62,22 +62,31 @@ chip soc/intel/pantherlake # Enable Energy Reporting register "pch_pm_energy_report_enable" = "true" - # As per document 813278, the Intel PTL-U 15W SoC supports - # Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System - # Agent (SA). The ICC Limit is represented in 1/4 A - # increments, i.e., a value of 400 = 100A. - # IA VR configuration + # As per document 813278, the following PTL SoC supports Fast + # V-Mode (FVM) on cores (IA), Graphics (GT), and System Agent + # (SA). The ICC Limit is represented in 1/4 A increments, + # i.e., a value of 400 = 100A. register "enable_fast_vmode[VR_DOMAIN_IA]" = "true" register "cep_enable[VR_DOMAIN_IA]" = "true" - register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A - # GT VR configuration register "enable_fast_vmode[VR_DOMAIN_GT]" = "true" register "cep_enable[VR_DOMAIN_GT]" = "true" - register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A - # SA VR configuration register "enable_fast_vmode[VR_DOMAIN_SA]" = "true" register "cep_enable[VR_DOMAIN_SA]" = "true" - register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A + register "fast_vmode_i_trip[PTL_U_1_CORE]" = "{ + [VR_DOMAIN_IA] = 63 * 4, + [VR_DOMAIN_GT] = 38 * 4, + [VR_DOMAIN_SA] = 38 * 4 + }" + register "fast_vmode_i_trip[PTL_U_2_CORE]" = "{ + [VR_DOMAIN_IA] = 38 * 4, + [VR_DOMAIN_GT] = 38 * 4, + [VR_DOMAIN_SA] = 38 * 4 + }" + register "fast_vmode_i_trip[PTL_H_1_CORE]" = "{ + [VR_DOMAIN_IA] = 75 * 4, + [VR_DOMAIN_GT] = 75 * 4, + [VR_DOMAIN_SA] = 38 * 4 + }" # Enable CNVi BT register "cnvi_bt_core" = "true" diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 92f561d6bf..53168ff662 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -345,12 +345,21 @@ struct soc_intel_pantherlake_config { bool cep_enable[NUM_VR_DOMAINS]; /* - * VR Fast Vmode I_TRIP threshold. + * Fast Vmode I_TRIP Thresholds for VR Domains + * + * This two-dimensional array represents the Fast Vmode I_TRIP thresholds + * for various Voltage Regulator (VR) domains across different power limit + * configurations in Panther Lake SoCs. + * + * The Fast Vmode I_TRIP threshold is used to override the default current + * threshold settings, ensuring optimal power management by adapting to + * specific VR domain requirements under different power limit scenarios. + * * 0-255A in 1/4 A units. Example: 400 = 100A * This setting overrides the default value set by FSPs when Fast VMode * is enabled. */ - uint16_t fast_vmode_i_trip[NUM_VR_DOMAINS]; + uint16_t fast_vmode_i_trip[PTL_POWER_LIMITS_COUNT][NUM_VR_DOMAINS]; /* * Power state current threshold 1. diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index bcdda8ed55..13401eb125 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -326,20 +326,20 @@ static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_in static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_pantherlake_config *config) { - for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) { - if (config->cep_enable[i]) { - m_cfg->CepEnable[i] = config->cep_enable[i]; - if (config->enable_fast_vmode[i]) { - m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i]; - m_cfg->IccLimit[i] = config->fast_vmode_i_trip[i]; - } - } - } - const struct soc_intel_pantherlake_power_map *map = get_map(config); if (!map) return; + for (size_t i = 0; i < ARRAY_SIZE(config->enable_fast_vmode); i++) { + if (!config->cep_enable[i]) + continue; + m_cfg->CepEnable[i] = config->cep_enable[i]; + if (config->enable_fast_vmode[i]) { + m_cfg->EnableFastVmode[i] = config->enable_fast_vmode[i]; + m_cfg->IccLimit[i] = config->fast_vmode_i_trip[map->limits][i]; + } + } + for (size_t i = 0; i < ARRAY_SIZE(config->thermal_design_current[0]); i++) { if (!config->thermal_design_current[map->sku][i]) continue;