From e54b82b85b0731682e72133df2ead96dc523e268 Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Tue, 9 Dec 2025 09:39:07 +0800 Subject: [PATCH] mb/google/ocelot/var/kodkod: Enable pcie_rp5 to allow proper enumeration of pcie_rp6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pcie_rp5 and pcie_rp6 belong to the same PCIe controller group (Port C1–C2). Within this controller, pcie_rp5 represents function 0 and pcie_rp6 represents function 1. For multi-function PCIe root ports, function 0 must be enabled for the controller to initialize fully. If only pcie_rp6 (function 1) is enabled, the controller does not complete initialization and the downstream LAN device fails to enumerate. Enabling pcie_rp5 ensures the PCIe controller group is brought up correctly and allows the RTL8111H LAN device behind pcie_rp6 to enumerate as expected. BUG=b:466908212 TEST=Build and boot to OS in kodkod. kodkod:/ # pclspci -v 01:00.0 Class 0200: Device 10ec:8168 (rev 15) DeviceName: Ethernet controller Kernel driver in use: r8169 Change-Id: I4332f3d612f1f66cd30dda7da723c47bcfce35a3 Signed-off-by: Ian Feng Reviewed-on: https://review.coreboot.org/c/coreboot/+/90422 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- src/mainboard/google/ocelot/variants/kodkod/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb index 264ff4db4c..03c12dd9db 100644 --- a/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/kodkod/overridetree.cb @@ -188,6 +188,9 @@ chip soc/intel/pantherlake device generic 0 on end end end # Gen4 M.2 SSD + + device ref pcie_rp5 on end + device ref pcie_rp6 on register "pcie_rp[PCIE_RP(6)]" = "{ .clk_src = 2,