From e4a809d441550913f5ffaecea861a29a7661e3d8 Mon Sep 17 00:00:00 2001
From: "Johann C. Rode" <jcrode@gmx.net>
Date: Fri, 28 Nov 2025 10:13:10 -0800
Subject: [PATCH] spd/ddr4: Double packageBusWidth of dual die package parts to
 16

This fixes an error I made in my previous commit 8a83b8625483 (spd/ddr4:
add parts), CB:90032. The package bus width for all the dual die parts
is indeed 16 rather than 8. This has been validated when porting
coreboot to the Lenovo Thinkpad X280 that uses soldered-on DDP RAM
(Samsung K4AAG165WB-MCRC).

Change-Id: I8baa7c979074584e65772315e66e787cef3202e4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
---
 spd/ddr4/memory_parts.json | 8 ++++----
 spd/ddr4/set-0/spd-11.hex  | 4 ++--
 spd/ddr4/set-0/spd-13.hex  | 4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/spd/ddr4/memory_parts.json b/spd/ddr4/memory_parts.json
index 7684401cdf..0d416f89fa 100644
--- a/spd/ddr4/memory_parts.json
+++ b/spd/ddr4/memory_parts.json
@@ -280,7 +280,7 @@
                 "CL_nRCD_nRP": 15,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
@@ -313,7 +313,7 @@
                 "CL_nRCD_nRP": 17,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
@@ -346,7 +346,7 @@
                 "CL_nRCD_nRP": 17,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
@@ -368,7 +368,7 @@
                 "CL_nRCD_nRP": 17,
                 "capacityPerDieGb": 8,
                 "diesPerPackage": 2,
-                "packageBusWidth": 8,
+                "packageBusWidth": 16,
                 "ranksPerPackage": 1
             }
         },
diff --git a/spd/ddr4/set-0/spd-11.hex b/spd/ddr4/set-0/spd-11.hex
index a29187c06a..9b760a7db7 100644
--- a/spd/ddr4/set-0/spd-11.hex
+++ b/spd/ddr4/set-0/spd-11.hex
@@ -1,11 +1,11 @@
 23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00
 00 00 08 09 F4 03 00 00 71 71 71 11 08 79 F0 0A
-20 08 00 05 00 A8 1E 2B 2B 00 78 00 14 3C 00 00
+20 08 00 05 00 F0 2B 34 2B 00 78 00 14 3C 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 EC B5 FE C3 C3 C3 C3 CA C1 00 00
+00 00 00 00 00 EC 9C B5 C3 C3 C3 C3 CA C1 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/ddr4/set-0/spd-13.hex b/spd/ddr4/set-0/spd-13.hex
index 4d300ee875..324eecb43f 100644
--- a/spd/ddr4/set-0/spd-13.hex
+++ b/spd/ddr4/set-0/spd-13.hex
@@ -1,11 +1,11 @@
 23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00
 00 00 07 08 F8 0F 00 00 72 72 72 11 00 72 F0 0A
-20 08 00 05 00 A8 1B 2B 28 00 78 00 14 3C 00 00
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 B5 D5 AC AC AC AC C1 D6 00 00
+00 00 00 00 00 00 9C B5 AC AC AC AC C1 D6 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00