From e4a129a6787103f0522f37024eed233a9ff9c7c7 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Sat, 27 Jan 2001 00:54:43 +0000 Subject: [PATCH] minor changes for via. You can build for vt5292A4 by: cd romimages/RON_VIA_SPD make Note that we now use 2.4.0 release multiple SDRAM do not work yet. --- src/northbridge/via/vt8601/raminitspd.inc | 11 +++++++++++ util/config/via.config | 9 +++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/northbridge/via/vt8601/raminitspd.inc b/src/northbridge/via/vt8601/raminitspd.inc index 53e51f3d31..f4b41d5b4c 100644 --- a/src/northbridge/via/vt8601/raminitspd.inc +++ b/src/northbridge/via/vt8601/raminitspd.inc @@ -18,7 +18,18 @@ register_table: .byte 0x64, 0xe4 /* slowest ram setting. banks 0, 1 */ .byte 0x65, 0xe4 /* banks 2, 3*/ .byte 0x66, 0xe4 /* banks 4, 5 */ +/* we tried increasing the drive, but that did not help or hurt. + * We will leave it at low drive for now, however. + */ +#if 1 +/* the standard BIOS goes for 0x5f here, which is very high drive. + * Try it out. RGM 1/26/1 */ +/* LOW DRIVE */ .byte 0x6d, 0x5 /* 0x4 = 24 ma on ma[2:13],we#, 24ma on ras# */ +#else + /* HIGH DRIVE */ + .byte 0x6d, 0x5f /* 0x4 = 24 ma on ma[2:13],we#, 24ma on ras# */ +#endif .byte 0x60, 0xff /* sdram in ALL banks. It's all we do. */ /* set these to 0xee (128 MB VC SDRAM). In our working code we set to * 0x88, but VIA code recommends 0xee. Since we are SPD, in the end, diff --git a/util/config/via.config b/util/config/via.config index bc64e26212..eeec45cdcc 100644 --- a/util/config/via.config +++ b/util/config/via.config @@ -8,7 +8,12 @@ mainboard via/vt5292 # Enable Serial Console for debugging option SERIAL_CONSOLE -linux /usr/src/linux +# Enable MicroCode update and L2 Cache init for PII and PIII +option UPDATE_MICROCODE +option CONFIGURE_L2_CACHE -option CMD_LINE='"root=/dev/hda1"' +# Path to your kernel (vmlinux) +linux ~/src/bios/linux-2.4.0-via + +option CMD_LINE='"root=/dev/hda1 single"'