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UPSTREAM: nb/intel/sandybridge/raminit: Do code cleanup

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Calculate the value from current DDR frequency.

Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).

Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/15184
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
(cherry-picked from commit d4c53e3fdd)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/354198
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Patrick Rudolph 2016-06-14 20:07:32 +02:00 • committed by chrome-bot
commit e31bcefad7
1 changed files with 3 additions and 6 deletions
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9
src/northbridge/intel/sandybridge/raminit.c
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@ -656,7 +656,6 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[0] = 18;
ctrl->timC_offset[1] = 7;
ctrl->timC_offset[2] = 7;
ctrl->reg_c14_offset = 16;
ctrl->reg_320c_range_threshold = 13;
} else if (ctrl->tCK <= TCK_933MHZ) {
ctrl->tCK = TCK_933MHZ;
@ -666,7 +665,6 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[0] = 15;
ctrl->timC_offset[1] = 6;
ctrl->timC_offset[2] = 6;
ctrl->reg_c14_offset = 14;
ctrl->reg_320c_range_threshold = 15;
} else if (ctrl->tCK <= TCK_800MHZ) {
ctrl->tCK = TCK_800MHZ;
@ -676,7 +674,6 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[0] = 14;
ctrl->timC_offset[1] = 5;
ctrl->timC_offset[2] = 5;
ctrl->reg_c14_offset = 12;
ctrl->reg_320c_range_threshold = 15;
} else if (ctrl->tCK <= TCK_666MHZ) {
ctrl->tCK = TCK_666MHZ;
@ -686,7 +683,6 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[0] = 11;
ctrl->timC_offset[1] = 4;
ctrl->timC_offset[2] = 4;
ctrl->reg_c14_offset = 10;
ctrl->reg_320c_range_threshold = 16;
} else if (ctrl->tCK <= TCK_533MHZ) {
ctrl->tCK = TCK_533MHZ;
@ -696,7 +692,6 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[0] = 9;
ctrl->timC_offset[1] = 3;
ctrl->timC_offset[2] = 3;
ctrl->reg_c14_offset = 8;
ctrl->reg_320c_range_threshold = 17;
} else {
ctrl->tCK = TCK_400MHZ;
@ -706,10 +701,12 @@ static void dram_timing(ramctr_timing * ctrl)
ctrl->timC_offset[0] = 6;
ctrl->timC_offset[1] = 2;
ctrl->timC_offset[2] = 2;
ctrl->reg_c14_offset = 8;
ctrl->reg_320c_range_threshold = 17;
}
/* Initial phase between CLK/CMD pins */
ctrl->reg_c14_offset = (256000 / ctrl->tCK) / 66;
/* DLL_CONFIG_MDLL_W_TIMER */
ctrl->reg_5064b0 = (128000 / ctrl->tCK) + 3;