From e2cf7abe0ad5f0bfbd7948b42a5762ae6eb73e54 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 11 Jun 2013 16:36:37 -0500 Subject: [PATCH] cpu: Add CPU microcode file to cbfs with 16-byte alignment On x86 there is a 16-byte alignment requirement for the addresses containing the CPU microcode. The cbfs files containing the microcode are used in memory-mapped fashion when loading new mircocode. Therefore, the data payload's address/offset of a cbfs file in flash dictates the resulting alignment. Fix this by processing the CPU microcode cbfs file separately as it uses $(CBFSTOOL) to find the proper location within the provided rom image. BUG=chrome-os-partner:20100 BRANCH=None TEST=Manually inspected cbfs layout: CBFS @ Offset 0x00700000 into 0x00800000 ROM size [0xfff00000] cmos_layout.bin type cmos layout (0x1aa) @ 0xfff00028, 0x48c (1164) bytes [0xfff004c0] pci8086,0406.rom type optionrom (0x30) @ 0xfff004f8, 0x10000 (65536) bytes [0xfff10500] cpu_microcode_blob.bin type microcode (0x53) @ 0xfff10560, 0x9c40 (40000) bytes [0xfff1a1c0] config type raw (0x50) @ 0xfff1a1e8, 0x157f (5503) bytes [0xfff1b780] fallback/vboot type stage (0x10) @ 0xfff1b7a8, 0x3ad3 (15059) bytes [0xfff1f280] (empty) type null (0xffffffff) @ 0xfff1f2a8, 0xcd8 (3288) bytes [0xfff1ff80] fallback/romstage type stage (0x10) @ 0xfff1ffe4, 0xa001 (40961) bytes [0xfff2a000] fallback/coreboot_ram type stage (0x10) @ 0xfff2a038, 0x15373 (86899) bytes [0xfff3f3c0] fallback/payload type payload (0x20) @ 0xfff3f3f8, 0xd00e (53262) bytes [0xfff4c440] u-boot.dtb type unknown (0xac) @ 0xfff4c468, 0x1e4b (7755) bytes [0xfff4e2c0] (empty) type null (0xffffffff) @ 0xfff4e2e8, 0x51cd8 (335064) bytes [0xfff9ffc0] mrc.bin type mrc (0xab) @ 0xfffa0000, 0x2d8b8 (186552) bytes [0xfffcd8c0] (empty) type null (0xffffffff) @ 0xfffcd8e8, 0x1e6d8 (124632) bytes [0xfffebfc0] spd.bin type mrc (0xab) @ 0xfffec000, 0x200 (512) bytes [0xfffec200] (empty) type null (0xffffffff) @ 0xfffec228, 0x13418 (78872) bytes Change-Id: Icc676a1c76c368d77e48cf573c6f846301da42a2 Signed-off-by: Aaron Durbin Reviewed-on: https://gerrit.chromium.org/gerrit/58238 Reviewed-by: Duncan Laurie Reviewed-by: Stefan Reinauer --- src/arch/armv7/Makefile.inc | 3 ++- src/arch/x86/Makefile.inc | 3 ++- src/cpu/Makefile.inc | 20 ++++++++++++++------ 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index feae76dc1d..974eeebee5 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -46,12 +46,13 @@ prebuild-files = \ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) # TODO Change -b to Kconfig variable. -$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \ -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \ -o $(CONFIG_CBFS_ROM_OFFSET) $(prebuild-files) true + $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a9bd1cb78e..2c6a5fcc1b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -61,11 +61,12 @@ prebuild-files = \ $(if $(call extract_nth,4,$(file)),-b $(call extract_nth,4,$(file))) &&) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) +$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(CBFSTOOL) $@.tmp create -m x86 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \ -B $(objcbfs)/bootblock.bin -a 64 \ -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) $(prebuild-files) true + $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else .PHONY: $(obj)/coreboot.pre1 diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 8d93756390..c5ec8dca33 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -12,17 +12,17 @@ subdirs-y += x86 ## Rules for building the microcode blob in CBFS ################################################################################ +cpu_ucode_cbfs_name = cpu_microcode_blob.bin + # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) -cbfs-files-y += cpu_microcode_blob.bin -cpu_microcode_blob.bin-type = 0x53 -cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +cpu_ucode_cbfs_file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +cbfs_include_ucode = y endif ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y) -cbfs-files-y += cpu_microcode_blob.bin -cpu_microcode_blob.bin-type = 0x53 -cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin +cpu_ucode_cbfs_file = $(obj)/cpu_microcode_blob.bin +cbfs_include_ucode = y endif # In case we have more than one "source" (cough) files containing microcode, we @@ -39,3 +39,11 @@ $(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -j .data -O binary $< $@ + +ifeq ($(cbfs_include_ucode),y) +# Add CPU microcode to specified rom image $(1) +add-cpu-microcode-to-cbfs = \ + $(CBFSTOOL) $(1) locate -f $(cpu_ucode_cbfs_file) -n $(cpu_ucode_cbfs_name) -a 16 | xargs $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 -b +else +add-cpu-microcode-to-cbfs = true +endif