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arch/x86: smbios write 7 table using deterministic cache functions

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This patch makes use of deterministic cache helper functions, for
example: cpu_get_cache_type(), cpu_get_cache_level() etc. helper
functions from arch/x86/cpu_common.c file.

Also, changed argument for get_number_of_caches() function that receives
cpu_get_max_cache_share() data directly.

Drop unused variables partitions, cache_line_size and number_of_sets as
struct cpu_cache_info.size  would provide the cache size directly.

TEST=Able to dump SMBIOS Table 7 with this CL, no changes seen in output.
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x0005, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE1
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 288 kB
        Maximum Size: 288 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Data
        Associativity: 12-way Set-associative

Handle 0x0006, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE1
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 192 kB
        Maximum Size: 192 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Instruction
        Associativity: 8-way Set-associative

Handle 0x0007, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE2
        Configuration: Enabled, Not Socketed, Level 2
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 1280 kB
        Maximum Size: 1280 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Unified
        Associativity: Unknown

Handle 0x0008, DMI type 7, 27 bytes
Cache Information
        Socket Designation: CACHE3
        Configuration: Enabled, Not Socketed, Level 3
        Operational Mode: Unknown
        Location: Internal
        Installed Size: 12288 kB
        Maximum Size: 12288 kB
        Supported SRAM Types:
                Unknown
        Installed SRAM Type: Unknown
        Speed: Unknown
        Error Correction Type: Unknown
        System Type: Unified
        Associativity: 12-way Set-associative

Change-Id: Iedbd3b745629dea57c3ad6b0d187eab2bcc3f7d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-07-23 21:02:45 +05:30
commit e2b5fee3b0
1 changed files with 12 additions and 34 deletions
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46
src/arch/x86/smbios.c
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@ -489,9 +489,8 @@ unsigned int __weak smbios_cpu_get_voltage(void)
return 0; /* Unknown */
}
static size_t get_number_of_caches(struct cpuid_result res_deterministic_cache)
static size_t get_number_of_caches(size_t max_logical_cpus_sharing_cache)
{
size_t max_logical_cpus_sharing_cache = 0;
size_t number_of_cpus_per_package = 0;
size_t max_logical_cpus_per_package = 0;
struct cpuid_result res;
@ -503,8 +502,6 @@ static size_t get_number_of_caches(struct cpuid_result res_deterministic_cache)
max_logical_cpus_per_package = (res.ebx >> 16) & 0xff;
max_logical_cpus_sharing_cache = ((res_deterministic_cache.eax >> 14) & 0xfff) + 1;
/* Check if it's last level cache */
if (max_logical_cpus_sharing_cache == max_logical_cpus_per_package)
return 1;
@ -797,30 +794,13 @@ static int smbios_write_type7_cache_parameters(unsigned long *current,
int *max_struct_size,
struct smbios_type4 *type4)
{
struct cpuid_result res;
unsigned int cnt = 0;
unsigned int cnt = CACHE_L1D;
int len = 0;
u32 leaf;
if (!cpu_have_cpuid())
return len;
if (cpu_is_intel()) {
res = cpuid(0);
if (res.eax < 4)
return len;
leaf = 4;
} else if (cpu_is_amd()) {
res = cpuid(0x80000000);
if (res.eax < 0x80000001)
return len;
res = cpuid(0x80000001);
if (!(res.ecx & (1 << 22)))
return len;
leaf = 0x8000001d;
} else {
if (cpu_check_deterministic_cache_cpuid_supported() == CPUID_TYPE_INVALID) {
printk(BIOS_DEBUG, "SMBIOS: Unknown CPU\n");
return len;
}
@ -828,17 +808,15 @@ static int smbios_write_type7_cache_parameters(unsigned long *current,
while (1) {
enum smbios_cache_associativity associativity;
enum smbios_cache_type type;
struct cpu_cache_info info;
if (!fill_cpu_cache_info(cnt++, &info))
continue;
res = cpuid_ext(leaf, cnt++);
const u8 cache_type = CPUID_CACHE_TYPE(res);
const u8 level = CPUID_CACHE_LEVEL(res);
const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1;
const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1;
const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1;
const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1;
const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets
* get_number_of_caches(res);
const u8 cache_type = info.type;
const u8 level = info.level;
const size_t assoc = info.num_ways;
const size_t cache_share = info.num_cores_shared;
const size_t cache_size = info.size * get_number_of_caches(cache_share);
if (!cache_type)
/* No more caches in the system */
@ -859,7 +837,7 @@ static int smbios_write_type7_cache_parameters(unsigned long *current,
break;
}
if (CPUID_CACHE_FULL_ASSOC(res))
if (info.fully_associative)
associativity = SMBIOS_CACHE_ASSOCIATIVITY_FULL;
else
associativity = smbios_cache_associativity(assoc);