diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h
index f43f75b692..a43132420c 100644
--- a/src/soc/intel/baytrail/baytrail/gpio.h
+++ b/src/soc/intel/baytrail/baytrail/gpio.h
@@ -334,7 +334,7 @@ struct gpio_bank {
 	const u8 gpio_f1_range_end;
 };
 
-void setup_soc_gpios(struct soc_gpio_config *config);
+void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap);
 /* This function is weak and can be overridden by a mainboard function. */
 struct soc_gpio_config* mainboard_get_gpios(void);
 
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h
index d2e7e62fbb..a8b5fdcc61 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/baytrail/ramstage.h
@@ -21,10 +21,11 @@
 #define _BAYTRAIL_RAMSTAGE_H_
 
 #include <device/device.h>
+#include <chip.h>
 
 /* The baytrail_init_pre_device() function is called prior to device
  * initialization, but it's after console and cbmem has been reinitialized. */
-void baytrail_init_pre_device(void);
+void baytrail_init_pre_device(struct soc_intel_baytrail_config *config);
 void baytrail_init_cpus(device_t dev);
 void set_max_freq(void);
 void southcluster_enable_dev(device_t dev);
diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
index 2ea4f142cd..5ea00a6bbe 100644
--- a/src/soc/intel/baytrail/chip.c
+++ b/src/soc/intel/baytrail/chip.c
@@ -69,7 +69,7 @@ static void enable_dev(device_t dev)
 /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
 static void soc_init(void *chip_info)
 {
-	baytrail_init_pre_device();
+	baytrail_init_pre_device(chip_info);
 }
 
 struct chip_operations soc_intel_baytrail_ops = {
diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h
index 0a57885b92..b312e40103 100644
--- a/src/soc/intel/baytrail/chip.h
+++ b/src/soc/intel/baytrail/chip.h
@@ -26,9 +26,10 @@
 #include <stdint.h>
 
 struct soc_intel_baytrail_config {
-        uint8_t sata_port_map;
-        uint8_t sata_ahci;
-        uint8_t ide_legacy_combined;
+	uint8_t enable_xdp_tap;
+	uint8_t sata_port_map;
+	uint8_t sata_ahci;
+	uint8_t ide_legacy_combined;
 	uint8_t clkreq_enable;
 
 	/* VR low power settings -- enable PS2 mode for gfx and core */
diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c
index 78aeb17570..33a556bf64 100644
--- a/src/soc/intel/baytrail/gpio.c
+++ b/src/soc/intel/baytrail/gpio.c
@@ -214,7 +214,7 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
 	}
 }
 
-void setup_soc_gpios(struct soc_gpio_config *config)
+void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
 {
 	if (config) {
 		setup_gpios(config->ncore, &gpncore_bank);
@@ -228,6 +228,14 @@ void setup_soc_gpios(struct soc_gpio_config *config)
 			setup_dirqs(*config->sus_dirq, &gpssus_bank);
 	}
 
+	/* Set on die termination feature with pull up value and
+	 * drive the pad high for TAP_TDO and TAP_TMS
+	 */
+	if (!enable_xdp_tap) {
+		printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
+		write32(GPSSUS_PAD_BASE + 0x2fc, 0xc);
+		write32(GPSSUS_PAD_BASE + 0x2cc, 0xc);
+	}
 }
 
 struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index e8f441f3c1..96229307aa 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -184,9 +184,9 @@ static void s3_resume_prepare(void)
 	s3_save_acpi_wake_source(gnvs);
 }
 
-void baytrail_init_pre_device(void)
+void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)
 {
-	struct soc_gpio_config *config;
+	struct soc_gpio_config *gpio_config;
 
 	fill_in_pattrs();
 
@@ -200,8 +200,8 @@ void baytrail_init_pre_device(void)
 	baytrail_run_reference_code();
 
 	/* Get GPIO initial states from mainboard */
-	config = mainboard_get_gpios();
-	setup_soc_gpios(config);
+	gpio_config = mainboard_get_gpios();
+	setup_soc_gpios(gpio_config, config->enable_xdp_tap);
 
 	baytrail_init_scc();
 }